chandhramohan
Member level 2
Hi Lee ,
The problem you are facing is a common problem .Some times the ATPG static simulation will pass & you will able to generate patterns .But same pattern simulation will fail in Verilog simulation , this could be because of your netlist library .There if you see there will path delay modelling specified in specify - end specify block .That can cause problem some times .
Only no-timing chk is not sufficient , have to take care of the unit delay .Which depends on the library .Try your VCS simulation using no-specify option .Even if its failing analyze ur simulation by picking the failing flop of the chains & chk if its failing during shift or capture .
I hope this gives some idea , how to debug .
Regards
Chandhramohan
The problem you are facing is a common problem .Some times the ATPG static simulation will pass & you will able to generate patterns .But same pattern simulation will fail in Verilog simulation , this could be because of your netlist library .There if you see there will path delay modelling specified in specify - end specify block .That can cause problem some times .
Only no-timing chk is not sufficient , have to take care of the unit delay .Which depends on the library .Try your VCS simulation using no-specify option .Even if its failing analyze ur simulation by picking the failing flop of the chains & chk if its failing during shift or capture .
I hope this gives some idea , how to debug .
Regards
Chandhramohan
I use the nospecify option , and simulation pass! 
