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Verilog Code optimization

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EDA_hg81

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How to optimize last person's verilog code for spartan-IIE.

Do you have any suggestions about how to optimize his code?

Such as use less <if else> etc....

Thank you.
 

One major thing is to avoid generating latch where it's unnecessary to reduce circuitry.There're several cases where unwanted latch is generated,for example, uncomplete case statement. Try seach google for complete information.
 

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    EDA_hg81

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