Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

need help for VGA timing description

Status
Not open for further replies.
E

EDA_hg81

Advanced Member level 2
Joined
Nov 25, 2005
Messages
507
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,808
vga timing

Please help me to find out the VGA timing description.
Can I realize two FPGA share one SDRAM by sharing the data bus and control bus of SDRAM?

Thank you
:cry:
 

gtf_v1r1.xls

You can try to impliment SDRAM controller in one FPGA and make interface to another one, or even something different let's say two fpga connected to one CPLD with SDRAM controller on it.
Sharing one SDRAm between two FPGAS your layout will complicated, and also you will need to have two SDRAM controllers which is resource waste, and somehow to sync those controllers

Good Lack!
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
vesa vga data timing

Thank you all.

this really helped me.:|
 

hwang-172.pdf

Hi, Gentlemen!
Does anybody remember VESA?
Study this document **broken link removed**
It will help you to calculate timing parameters for any resolution.

GTF means "Generalized Timing formulae".

Regards, YUV.
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
vga timing parameters

YUV,


Do you have user name and password for the VESa site.


Thanks,
 

gtf vga timing

Iouri said:
YUV,
Do you have user name and password for the VESa site.
Thanks,
Click to expand...
No, I don't. But the folder /public/ is opened for everybody.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top