Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

D-latch's propagation time?

Status
Not open for further replies.

davyzhu

Advanced Member level 1
Joined
May 23, 2004
Messages
494
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Location
oriental
Activity points
4,436
Hi all,

When I use positive level trigger D-latch, What's the propagation time for D-latch?
I.e. from positive edge or from negative edge?

Any suggestions will be appreciated!
Best regards,
Davy
 

ok when u consider a positive edge triggered register propagation delay,

consider that the setup time and hold time constraints are meet, the time taken for D to be copied to Q(output) this is defined as propagation delay. maximum delay is propagation delay.

minium delay is refered to as contamination delay..

Tcq - propagation delay

Tcd- Contamination delay.

T - time required for the proper operation of the sequential circuit.

Tplogic+Tcq+Tsu >= T

Tsu - setup time

Thold> Tcdregister+TcdLogic.

these are the various timing metrices for any sequential circuit.

The maximum delay is the propagation delay with reference to setup time

and the minimum delay is the contaminationa delay with respect to hold time.

with regards,
 

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
What is the contamination delay
 

contamination delay is the minium delay.. Tcd

with regards,
arun
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top