Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Anyone use inverter for clock tree synthesis(in astro)?

Status
Not open for further replies.
albred

albred

Member level 2
Joined
Aug 1, 2005
Messages
48
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Location
china
Activity points
1,682
clock tree synthesis

It's said that using inverter instead of buffer has a lot of advantages such as reducing insertion delay,skew,power,leakage current,process violation(P variance)...
Who can tell me the practical effect of using this techonology?I got larger insertion delay by using inverter in astro:cry:
 

inverters in clock tree

the inverter you used is normal inverter? not for clock?
 

use buffers or inverters for clock tree

surely clock inverter.
maybe i find the answer:
the stdcell library is TSMC18_6ml,and I find that the intrinsic delay of CLKBUFs is about 0.06-0.09ns,while the intrinsic delay of CLKINVs has a jump from 0.018ns(CLKINVX8) to 0.14ns(CLKINVX12).
 

advantages of inverter in clock tree

I think you are right. We could also used clock inverters in clock tree. The same thing.

And as far as I know, it is typically used in the inverted clock(Synopsys tool could handle it). What we gain if we use clock inverter instead of clock buffer? In the case you described it seems that the clock inverter provide more acurate timing step (0.018ns) than the clock buffer(0.06) so that the clock skew could be less.

But I could not find any advantage in delay, power, leakage or process viariance. Anyway, from transistor level, we could see all this parameters are decided by design of the cells. Let me know if you have some ideas about it...
 

inverter and buffer in clock tree synthesis

luancao said:
I think you are right. We could also used clock inverters in clock tree. The same thing.

And as far as I know, it is typically used in the inverted clock(Synopsys tool could handle it). What we gain if we use clock inverter instead of clock buffer? In the case you described it seems that the clock inverter provide more acurate timing step (0.018ns) than the clock buffer(0.06) so that the clock skew could be less.

But I could not find any advantage in delay, power, leakage or process viariance. Anyway, from transistor level, we could see all this parameters are decided by design of the cells. Let me know if you have some ideas about it...
Click to expand...

it's intrinsic delay,not timing setup.
Building inverter clock tree would use less FETs than building buffer clcok tree to get the same target skew(1 buffer = 2 inverter).so it would get less delay,power...
 

clock inverters

As you know, why do we use buffers in clock tree? That's because we want to balance the skew to the CK pin of each DFF and also provide a reasonable drive strength at the CK pin of DFF.

Let's assume two inverters in the clock inverters is equal to one buffer in the clock buffers in size, power, delay etc. e.g. INVx 0.01ns delay, 0.01mW power, 0.01uA leakage, while BUFx 0.02ns delay, 0.02mW power, 0.02uA leakage. And now the latency in the clock tree is, say, 1ns. If you use the INVx, you need 100 INVx, you get 1ns delay, 1mW power consumption, and 1uA leakage. If you use BUFx, you need 50 BUFxs, you also get 1ns delay, 1mW power consumption, and 1uA leakage. more or less the same thing....?
 

clock tree synthesis faq

minimization latency is another target,so your supposition is not reasonable.
in fact a buffer is not equal two inverter,the front inverter is aways larger than the last.

here is an article about inverter Vs. buffer.enjoy it.
 
i am also very interested in the clock buffer tree and clock inverter tree
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top