Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design Issue for C-2C Ladder Based DAC

Status
Not open for further replies.

snoop835

Advanced Member level 4
Joined
Feb 7, 2005
Messages
102
Helped
6
Reputation
12
Reaction score
3
Trophy points
1,298
Location
Penang, Malaysia
Activity points
1,371
c-2c ladder

Hi all,

I want to design 8-bit C-2C Ladder Based DAC. The journal is attached for review.

From the journal (fig. 3), how do I implement the switches and what is the timing requirement for the switches? My thought is, for each of the capacitors, use 3 NMOS switches (one is connected to capacitor and vin with Gate connected to CLK1, the other switch is connected to capacitor and vref/2 with gate connected to the DAC's input bits, the last switch is connected to capacitor and gnd with gate connected to inverted DAC's input bits)

How do I decide the value for the capacitor? What's the reasonable value for the capacitors?

Anyone has a good reference in this topic?

Thanks in advance
 

c-2c dac

please refer to P.E allen's book.
 

    snoop835

    Points: 2
    Helpful Answer Positive Rating
c 2c ladder layout

Hi piao,

What is the topic for the book? Where can I get it?
 

c-2c capacitor

cmos analog circuit design second edition
by Phillip E. Allen Douglas R. Holberg

snoop835 said:
Hi piao,

What is the topic for the book? Where can I get it?
 

    snoop835

    Points: 2
    Helpful Answer Positive Rating
c 2c ladder cmos

hi snoop835:
i havn't enough points,can you send me ?
my mail :cceenn@126.com
thank you.
 

inverted c-2c dac

snoop835 said:
Hi all,

I want to design 8-bit C-2C Ladder Based DAC. The journal is attached for review.

From the journal (fig. 3), how do I implement the switches and what is the timing requirement for the switches? My thought is, for each of the capacitors, use 3 NMOS switches (one is connected to capacitor and vin with Gate connected to CLK1, the other switch is connected to capacitor and vref/2 with gate connected to the DAC's input bits, the last switch is connected to capacitor and gnd with gate connected to inverted DAC's input bits)

How do I decide the value for the capacitor? What's the reasonable value for the capacitors?

Anyone has a good reference in this topic?

Thanks in advance

It base on your requirement of compent mismatch which will effect your ADC performance, you must contact your process engineer to find the best value of capacitor under your accuracy requirement
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top