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Worst case corners combination in CMOS process

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Hello

Below is the set of worst-case corners defined by AMS technology,
corners.PNG



typical >(TM)
worst case speed > (WS)
worst case power >(WP)
worst case one > (WO)
worst case zero >(WZ)

In reality, a huge number of the combination is possible making simulation with corners approaching the Montecarlo counterpart, in the other hand reducing the number of combination makes verification less realistic to the real.

AMS suggested the above table as worst-case ever condition, so validating design on this corner will assure the expected yield.

Here I am not discussing the accuracy of the above table, my question is that combination based on the AMS only technology or I can use this combination for any different technology

Thank you

Best Regards
 

That's why you have corner simulations in cadence adexl. YOu run all combinations and you pick the worst one for your circuit and parameter of interest.
 
Dear Suta,

you are right, every combination is possible, the only thing I can't understand is that how could be in the same chip the resistor is in WP condition while for example capacitor is in WS condition,
I presume that all the wafer must have the same corner condition for all the component,

yes I believe that due to oxide thickness ditribution there will be differences in Vth, but this again shouldn't make some transistors as WP and other as WS
 

We are not talking here for variations in the NMOS only or among NMOS only. If someone at the fab cooks the recipe such that NMOS come fast and PMOS slow, well that's how it is. These happen at different steps of the process and it is not impossible. Same for resistors and capacitors.
 
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