Sizing of Transistor in Analog Layout

impact ionization

Hi ALL,

Why is that in ANALOG LAYOUT the length of the gate is chiosen 2-5 times bigger thatn the minimum size . In one of the circuits the lenght was taken 5um while the technology used was 0.35um.

Is there any particular reason for choosing that way or the reason is because of fabrication


Thanks in Advance

how to reduce channel length of a transistor

You do that to avoid shaort channel effects which transistor suffer in small length devices
You could read on short channel effects for more indepth idea.
Also for good matching, we try to have larger W and L' the minimum

short channel effects+impact ionization+edaboard

To minimize the channel length modulation.In this case , the circuit won't be effected not so much supply voltage variations.

analog circuit layout sizing

A reason is for performace,The larger the size,the less the noise.

delta w and delta l effect in layout

Dear Prasanna,

The earlier people have said all the things I wanted to say. But let me sum things up.
You want bigger lengths because
1. We want to avoid Channel Length modulation effects
2. We want to avoid Threshold voltage changes for submicron devices due to small channel
3. Lower 1/f noise for input differential pairs.
4. Other short channel effects like Velocity saturation, impact ionization, etc.

Because of all these effects modeling of transistors using the basic equations has become really complicated. Using larger lengths also makes sure that we still adhere to the square law

analog layout matching

Hi Guys Thanks a Lot !!

This discussion has cleared most of the issues. Really this site is really wonderful for people like me in VLSI.

Once again thanks a lot

see this

I'd like to add that using 2~5 times the minimum L is mainly for low frequency circuits. For RF, it is common to use the minimum L for the signal devices (means input transistor) and large L for the current sources. The reason is that a smaller L give a faster device and smaller input capacitance, so the circuit can work at frequency of ~GHz order. You can refer to many LNA or mixer article.

to avoid channel length modulation

There are many reasons to have L greater than minimum:

several have already been discussed here, I would also include:

- Need for large ratio of W/L from 1 transistor to W/L of another. If you need large ratio, but do not care so much about the accuracy of the ratio: Example- if you need 400:1 ratio, you can make one transistor 20u/1u and the other 1u/20u.

- Creating a small W/L. You might do this if you need to allow a larger range of voltages for the transistor to operate in linear region, for example.

- Reduce the sensitivity to delta-L- the change in length from the foundry. If you are on 1u minimum length, you might have a delta-L of 0.4u. This means that a device with a drawn (specified) length of 1u might be as short as 0.6u or as long as 1.4u (this would typically be the same across the chip).

- Voltage standoff. At short channel lengths, fields can punch-thru the "off" channel and open a conductive path from source to drain. Longer devices will help remedy this.

- Reduction of leakage currents. On a sample-and-hold, for example. Short channel devices tend to have more leakage current than longer channel devices.

I have a doubt.. Is it possible without any side effect to layout such a big transistor like 400u/0.35u ???
What are the issues tobe taken care...
thanks in advance

Normally for an extreme W/L like 400u/0.35u, the layout will be done with multiple smaller transistors.

Typically, this would be done with stripes (example 20 stripes, each of 20u width).

It can also be done with a waffle structure, but you have less assurance of the actual width or W/L that you get.

If you are using an extreme width in order to get a ratio, you may be able to vary width in one transistor and length in another. Due to delta-L, delta-W and threshold differences between long and short, wide and narrow devices, the matching will not be real good, but you can obtain an inaccurate real large ratio fairly easily:

Example need 400:1. You could use a device that is 400u/0.35u and another that is 1u/0.35u to get this ratio. You could also use a device that is 20u/0.35u and a second device that is 1u/7u to get the same ratio. The chip area would be 140u^2 for the first option, but only 14u^2 for the second. The matching will not be as good for the second, due to delta-L mostly, but it would work.

In reality, you would probably use either 401 unit 1u/0.35u devices with 400 in parallel for the 400u wide device, or you would use 40 unit 1u/0.35u devices, with 20 in parallel for the 20u/0.35u and 20 in series for the 20u/7u device.

Long channels especially used in current mirrors to reduce lambda effect .
As lambda inversely proportional to L .Large area less is the mismatch.

Addressing skyismylimit question :I think Gate resistance would be the major factor considered while doing layout for large transistor .