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CMOS fabrication - why do we use a p+ substrate trap and n+ well trap ?

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94d33m

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I have tried searching google about this, and Im surprised to see no matching results on this trap thingy...
 

Re: CMOS fabrication - why do we use a p+ substrate tap and n+ well tap ?

Silicon substrate and well themselves in fact are relatively highly doped material, but for a good (low-ohmic) contact to metal you want it even higher doped - that's why these Si-Metal contact regions get additional high(+) implant doses.

BTW: These contacts are called tap, not trap - think of a water tap! Traps are for mice :wink:
 
I think "tap" - a region where metal interconnects (metals / contacts) are brought in electrical contact with wells and substrate - includes both active (diffusion, OD, moat,...) mask and n+ or p+ mask.
This forms a highly dopes silicon regions right under the contacts (or under silicide - a metal-like material formed on the top of silicon), enabling an efficient tunneling through the Schottky contact, and hence providing a low-resistive, Ohmic contact.

"Ohmic contact" is an idealization meaning that the voltage applied to the metal is "transferred" directly to semiconductor region (a quasi-Fermi potential) without any voltage loss (no voltage drop) at the interface.

Max
 
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