2-state Buffer with buffer

2-state Buffer with enable

Hello,

I have a question that is there any circuit that only inverts the o/p signal when enable is high other wise it should behave as a normal buffer.

The truth table is
E = Enable
A = Input
X = Output
E A X
0 0 0
0 1 1
1 0 1
1 1 0

The output is Enable dependent. There may be more complex logic to do that but I am trying to reduce the current design and I want to perform this function with less then 8 transistors.

If this is not possible with less than 8 transistors then can any one guide me with Latch circuitry for this logic.

E1 = Enable 1
E1 = Enable 2
A = Input
X = Latched Output
The possible values are

E1 E2 A X
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1

All other inputs will be invalid. This logic can be implemented with up to 20 transistors.
Thanks

the first logic is XOR. that is simple. the number of transistors depends whether you already have A and Abar, E and Ebar.

I am not sure I understand the second one, the 'latch'. what is the meaning of E1 and E2?

Hi,

I have a question that is there any circuit that only inverts the o/p signal when enable is high other wise it should behave as a normal buffer.

The truth table is
E = Enable
A = Input
X = Output
E A X
0 0 0
0 1 1
1 0 1
1 1 0

Click to expand...

ENABLE is not the correct name. It usoften used to switch OFF/ON something. For example to make an output high-Z.

You have just two equal inputs and one output. Your logic is called XOR gate.

*********

If this is not possible with less than 8 transistors then can any one guide me with Latch circuitry for this logic.

E1 = Enable 1
E1 = Enable 2
A = Input
X = Latched Output
The possible values are

E1 E2 A X
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1

Click to expand...

Here we have missing informations:
With three inputs there are 8 possibke combinations, but you show only four.
Additionally a two state output can only be high or low, but not "invalid".

A latch is similar to a memory cell. It can "freeze" it's state...but this is never shown in your truth table.

Klaus

ThisIsNotSam said:

the first logic is XOR. that is simple. the number of transistors depends whether you already have A and Abar, E and Ebar.

I am not sure I understand the second one, the 'latch'. what is the meaning of E1 and E2?

Click to expand...

Thank you for ur help. Yes the logic is XNOR, but XNOR has 2 inputs , while I have 1 data input and other is just the enable to invert the data or not. In the 2nd logic , by latch I mean I want to keep the state output state constant depending on the input logic. E1 and E2 are Enable 1 and 2 that are independent of each other. When E1 is active Then data input 'A' will appear at output 'X' and when When E2 is active the inverse of data input A is appear at 'X'

KlausST said:

Hi,



ENABLE is not the correct name. It usoften used to switch OFF/ON something. For example to make an output high-Z.

You have just two equal inputs and one output. Your logic is called XOR gate.

*********

Here we have missing informations:
With three inputs there are 8 possibke combinations, but you show only four.
Additionally a two state output can only be high or low, but not "invalid".

A latch is similar to a memory cell. It can "freeze" it's state...but this is never shown in your truth table.

Klaus

Click to expand...

Thank you for ur help. Yes the first logic is similar to XOR. but I need 2 states at O/p not the 3 states. The o/p should be inverted if Enable is high. If enable is low , then It should act as a buffer.

In the 2nd logic, Only the shown 4 configurations are valid for the circuit and yes I am working with NVM design and I want to freeze o/p logic when E1 or E2 gets enabled.

Hi,

Thank you for ur help. Yes the logic is XNOR, but XNOR has 2 inputs , while I have 1 data input and other is just the enable to invert the data or not.

Click to expand...

Again:
The first is XOR, it has two inputs and one output.
Your terminology of ENABLE is wrong. It is just another digital signal with 0 and 1 only.

Your truth table shows exactely XOR. And the XOR gate doesn't care about the names of the input signals. You may call them as you like. Each input signal has exactely two states 0 and 1, and the output has two states 0 and 1, too.

Klaus

Since we are talking about terminology, it is worth mentioning that naming an output X doesn't help either. Very confusing.
And the truth table can express time dependency. Say for a flip flop, we usually say Q(t) = Q(t-1) or similar

And about the 'latch' case, what are you expecting to happen when both E1 and E2 are 0 or 1?

I think the latch case is for E1 & E2 both 0's which would be Q(t) = Q(t) (or X(t) = X(t) in the OPs naming). They neglected to show this though.
Have no clue what the behavior would be for E1 & E2 both 1's. Maybe just let the input straight through?