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Deep NWell for NMOS is connected to VSS, how to connect the floating substrate

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emc_analog

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Hi all,

I have generated a circuit with deep nwell NMOS devices so that the NMOS is isolated from the rest of the substrate. The NMOS body is connected to "VSS". Now the problem is how to connect the floating substrate to a different ground node and how to name it so that it clears DRC and LVS.
 

To isolate the NMOS devices from the substrate you should connect the deep nwell to VDD instead of VSS. Substrate is to be connected to VSS (resp. GND).
 

Hi Eriki,

sorry let me rephrase my question as u have inadvertently caused some confusion. My question is about a deep Nwell NMOS (nmos3v3dnw) for which I have connected the deep nwell to VDD and the NMOS body to VSS. Now there is a psubstrate outside the deep n well NMOS which is floating. If I connect this floating psubstrate to the same VSS node then their is no problem and LVS/ERC is perfectly clean. But if I don't want to connect it to the same VSS terminal the reason being I don't want the substrate noise from the external psubstrate going into the isolated Pwell of the deep n well NMOS(nmos3v3dnw). What should I do then ?
 

Your question has come up often on this board and elsewhere. You need two separate VSS until you short them at the VSS pad. Some use VSSA & VSSD. Your circuit in the dnwell can use VSSA and other circuits that are in the substrate can be tied to VSSD. At the top level of your schematic the subcircuits both get tied to VSS at the pad.

Alternatively, you can use a small metal resistor off the pad to isolate the two VSS.
 

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    wanderland

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I think rangermad showed good solutions. Additionally, one could use 2 different VSS pads (if possible) and provide them with 2 different GND supplies to further separate the sensible VSS regions from the noisier ones.

@dragonfury: I responded to emc_analog's post (none other was visible for me), where the problem wasn't so clearly shown, I think. Sorry for any confusion.
 

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