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DRC Error Edge not on grid

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MahmoudHassan

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Hello :)
I designed a simple NAND Circuit and used it in Half adder circuit, and even though the nand layout had no DRC errors when I used it I got 328 Edge not on grid error !!! and all of them was about my nand cell !
How can I solve this error in virtuoso i am using the simple Diva tool.

Best Regards
pp.jpgp.jpg
 

You probably didn't use the correct grid recommended by the SCMOS rules. Change it correspondingly.
 
Is your nand gate placed off grid?
 

You probably didn't use the correct grid recommended by the SCMOS rules. Change it correspondingly.

I am using NCSU_0.6ami free PDK
This problem didn't appear with other circuits like inverter, nand, nor and I didn't change anything related to grid spacing ???!

- - - Updated - - -

Is your nand gate placed off grid?

I run DRC on nand circuit by itself and there were no errors
after using it inside half adder and run DRC test I got these errors
 

I run DRC on nand circuit by itself and there were no errors
after using it inside half adder and run DRC test I got these errors

That is way I think you may have it placed off grid inside the half adder.
 
I run DRC on nand circuit by itself and there were no errors
after using it inside half adder and run DRC test I got these errors

I can't tell you why this occurred. But I'd suggest the following: First compare the grid sizes of the "good" and the "bad" layout. If they are the same, check their sub-grid division ratios (there are different ones: 4, 5, 8, 10). If they also fit together, I'd recommend one of the following methods:

1. Try and find a SKILL program which sets all non-grid points to the next valid grid point. Not just the most elegant method, but it works. I remember I've used this program once or twice (but don't have it any more, unfortunately).

2. Copy your "good" nand layout to a different name, then create the half adder once more.

Good luck!
 
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