Is this rtl synthesis flow right ?

I'm a rtl engineer. I'm confused between the difference of sdf and spf back annotation. As I know sdf came from STA( PT) and SPF came from STAR-RC. So In my experiance, the sdf used to timing close the netlist without RC elements. then this netlist to send a PNR team. After extraction RC elements in layout team by starRC. Then finally we once again do post sim with spf(a.k.a back annotation) .

Is this rtl synthesis flow right ? Then where is to do CTS flow?

Here is typical design flow that I can tell you. It is depended Company business and set of EDA tool which they are using.
-------
RTL:
- No timing sim

Synthesis:
+ Input : RTL, Constraint and library
+ Output:
- Netlist
- Ideal clock STA report. ( Synthesis doesn't optimize clock delay, this optimization will be done at CTS step in PnR team)
- So delayed sim ( with SDF ) has less meaning because clock delay has not been touched.
- Logical Functions of netlist can be confirm to be equivalent with RTL by Formality or Conformal ... tool.

PnR: ( Place and Route )
+ Input: Netlist, constraint, PnR libraries ...
+ Output:
- Full clock delay STA report ( Propagated STA ) - This is Timing Sign-off
- Parasitics delay ( SPEF ) which you can convert to SDF also.
- Logical Functions of netlist can be confirmed to be equivalent with RTL ( synthesis netlist ) by Formality or Conformal ... tool.
- SDF sim - This is Functional Sign-Off.

Clock Tree Synthesis ( CTS ):
- Netlist --> Placement --> CTS --> Routing
- Each step has optimization in timing, area, DRC reduction ...

Functional sign-off must be done with netlist and delay from final PnR design.

slutarius said:

Here is typical design flow that I can tell you. It is depended Company business and set of EDA tool which they are using.
-------
RTL:
- No timing sim

Synthesis:
+ Input : RTL, Constraint and library
+ Output:
- Netlist
- Ideal clock STA report. ( Synthesis doesn't optimize clock delay, this optimization will be done at CTS step in PnR team)
- So delayed sim ( with SDF ) has less meaning because clock delay has not been touched.
- Logical Functions of netlist can be confirm to be equivalent with RTL by Formality or Conformal ... tool.

PnR: ( Place and Route )
+ Input: Netlist, constraint, PnR libraries ...
+ Output:
- Full clock delay STA report ( Propagated STA ) - This is Timing Sign-off
- Parasitics delay ( SPEF ) which you can convert to SDF also.
- Logical Functions of netlist can be confirmed to be equivalent with RTL ( synthesis netlist ) by Formality or Conformal ... tool.
- SDF sim - This is Functional Sign-Off.

Clock Tree Synthesis ( CTS ):
- Netlist --> Placement --> CTS --> Routing
- Each step has optimization in timing, area, DRC reduction ...

Functional sign-off must be done with netlist and delay from final PnR design.

Click to expand...

Thanks,
Would you let me know more about you said Synthesis?
I am confused that Synthesis's ouput have Netlist which is Ideal Clock STA(Synthe sis doesn't optimized clock delay), but what about delayed sim? What kinds of delay are simulated in here?

Please let

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Is this right? In briefly,

Presim : SDF(from PT) + Netlist(from DC)
Postsim : POST SDF(from SPEF) + POST Layout Netlist

While back annotating, will we go to the synthesis stage? Can we use the sdf obtained from the PnR stage and give it as an input to the synthesis tool because this sdf/spef contains the actual delays due to RC also? Will such a resynthesis method give us a better optimized result?

SPEF is included an information of post layout netlist so we don't need to go back synthesis stage but if we have to use post SDF then we have to get it from SPEF. Also CTS is needed while back annotation.

Would you let me know more about you said Synthesis?
I am confused that Synthesis's ouput have Netlist which is Ideal Clock STA(Synthe sis doesn't optimized clock delay), but what about delayed sim? What kinds of delay are simulated in here?
--> There is no need to simulate the netlist with delay here. You can confirm the function by formal verification. That is enough at after synthesis.

Please let

- - - Updated - - -

Is this right? In briefly,

Presim : SDF(from PT) + Netlist(from DC)
Postsim : POST SDF(from SPEF) + POST Layout Netlist

There is no term like "PreSim" or "PostSim" in ASIC design flow.
Pre or Post is used to mention about the "state" of design.

Below can be a reference, you can put Pre or Post into each of them from Synthesis:
RTL - Synthesis - DFT insertion - Place - CTS - Route.

So, I dont understand what is your question regarding to Presim or Postsim. Sim is just an action on design flow, not a specific state.

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biju4u90 said:

While back annotating, will we go to the synthesis stage? Can we use the sdf obtained from the PnR stage and give it as an input to the synthesis tool because this sdf/spef contains the actual delays due to RC also? Will such a resynthesis method give us a better optimized result?

Click to expand...

There is a feature from Synopsys that allow you to use the Layout information from PnR as input for synthesis phase.
It reduce runtime, more optimization on congestion, timing ....

You can investigate it on Synopsys site. I dont know other EDA vendors have this feature or not.