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[SOLVED] convering fuction in vhdl

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sam93

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hi, i face to a problem when compiling below code in ise.
would you help me?

error is : Line 17. conv_integer can not have such operands in this context.

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
 
entity dc1 is
   port (
   in1 : in std_logic_vector(15 downto 0);
   in2 : in std_logic_vector(15 downto 0);
   output : out std_logic_vector(15 downto 0)
   );
   end dc1;
   architecture Behavioral of dc1 is
   signal in1_int, in2_int, output_int: integer range 0 to 16;
    function CONV_INTEGER(ARG: SIGNED) return INTEGER; 
   begin
   in1_int <= conv_integer(in1);
   in2_int <= conv_integer(in2);
   output_int <= in1_int/in2_int;
   output <= std_logic_vector(to_signed(output_int,output'length));
   end Behavioral;
 
Last edited by a moderator:

You have to give signed argument for the conversion
I think this may solve the error

Code: 
in1_int <= conv_integer(signed(in1));

But I think instead of conv_integer you have to use the to_integer function
please see the below link
http://www.xilinx.com/support/answers/45213.html
 
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    sam93

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There are problems here because you have included both numeric_std and std_logic_arith in your code. They both define signed and unsigned types - causing a conflict that means you cannot see either type without directly using them.

The solution is to remove std_logic_arith as it is not a standard VHDL library anyway. This will mean you will have to convert to std_logic_vector via the to_signed() function, and conv_integer will not be available.

On another note: why have you declared a local conv_integer function? you have not defined a body for it - and it will override the conv_integer function in the std_logic_arith library.
 
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