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[SOLVED] Basic synthesis questions

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limitless_21

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Hi Guys,

wanted to know a few answers to the few basic questions:

> why do we require library before elaboration step during logic synthesis ? When we are saying that it before mapping all the stages are technology independent.
> What are all the techniques used for internal optimisation ?
> How are setup and hold timings being resolved during synthesis.?
> How is a setup violation and a hold violation detected in a circuit.?
> Please provide me the guidelines for RTL designing interview also

Thanks
Limitless_21
 

we require general library, to map RTL to gates
delay optimization
setup are resolved by optimizing the path and hold are not touched
refer to manual
learn verilog and synthesis
 

1- the goal of a synthesis tools is to tranform RTL in netlist, so the tools require as input at minimum a and and flop. The elaboration step is only a first stage and do not need any stdcell.
2- tools could replace flops with constant input, stuck value, reorganise the pipeline..
3- see responce provided by mail4idle2
4- what do you mean by detected by the circuit? if any of these violation occurs on the real chip, the functional behavior will not any more guarantee. STA is here to check that.
5- see previous responce.
 

One last question comes up as it is well known that elaboration step is technology independent step, but then if we see in a practical world like suppose RC tool - the flow in the tool goes this way :

read library
read hdl
elaborate
synthesize -to_generic
read sec...... and so on

In this case if we remove the library and then run the design in RC it will throw an error, Stating that library was not being defined by the user.
So in this case how can we justify the above statement of the technology independent step during elaboration

Thanks
limitless_21
 

Nice thought, if you try u will be able to parse the RTL (i.e. read_hdl) without loading the libs. Elaborate builds the design and since synthesis is supposed to map to the library this is required.
Furthermore if you have any macro's etc instantiated it would need the .lib files to build the design and hence elaborate requires the lib files to be there.

Again after elaboration if you export a netlist it will be technology independent.
 
There are certain flows where you do analyze_libs first and then do analyze RTL. That itself shows the imortance.
One of the basic requirement of synthesis is to 1st make the RTL into boolean logic (stored in intermediate files) and then map it to available logic cells in library and finally assign it a gate.
Ex: RTL has assign statement or always @posedge etc... that even you can infer logically refers to an AND gate hose output is connected to an OR gate say.. Now in your library it will see that it has an AND+OR gate (ONA2X20) so the tool will assign it that cell. You can always dump out a netlist at the end of elaborate stage and check... it gives a perfect representation of the RTL/HDL. Thereafter it is optimized.
 

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