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VHDL Array Declaration in port

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rourabpaul

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I have googled with this topic but didnt get any ultimate solution. Can i declare a array as a port??
 

if the type exists in the current namespace, then yes.

Practically, this means making a package with the correct types, and then "use" the package in each file that needs it.

Code: 
package my_types_pkg is
  type array8 is array (natural range <>) of std_logic_vector(7 downto 0);
end package;

and then in each file:
Code: 
library work;
use work.my_types_pkg.all;

the same applies to most VHDL types -- otherwise even std_logic_vector wouldn't be allowed as a port.
 
@permute can we use a generic parameter inside the package. I like to state from your example above.
Code: 
package my_types_pkg is
  type array8 is array (natural range <>) of std_logic_vector(data_length downto 0);
end package;
use work.my_types_pkg.all;
Entity blk1 is 
Generic (data_length := 18);
port(
       ...... 
);
End blk1;
 

Which generic are you referring to? and how/why would you want to use a generic in a package?

VHDL 2008 does have package generics, but 2008 isnt very well supported.
 

@TrickyDicky My example scenario is shown below. My output port is an array, so I think the only way is to have a package which defines about my array. I wanted the user to have control over deciding the number of vectors in the array. So how can i make this constant value 17, defined inside the package, to be replaced by a parameter which user can define it ?
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

PACKAGE heap_arr_pkg IS
    type array_UI is array (natural range <>) of signed (17 downto 0);
END; 

USE work.heap_arr_pkg.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY comp_heap IS
-- Declarations
GENERIC(   data_width : positive := 18;
                array_width: positive := 49;   
                cnt_width   : positive := 15);
PORT(
      clk    : IN     std_logic;
      rst    : IN     std_logic;
      en     : IN     std_logic;
      addr  : IN     unsigned (15 downto 0);
      heapout: OUT    array_UI (array_width downto 0)
     
    );
END comp_heap ;
 
Unfortunately, in VHDL 93, you cannot do that. You would need to declare a constant in the package and let the user modify that.

With 2008, you can declare the array in a package like this:

type array_UI is array( natural range <> ) of std_logic_vector;

and then use it like this:

heapout : out array_UI(a downto 0)(b downto 0);

But as I said before, 2008 is not very well supported (Quartus can do this feature at least).
 
Yes, and vhdl2008 also supports having types as generics. then UI can be std_logic/signed/unsigned/records/etc...

I'm not sure what the issue is. You can have the generic control the number of vectors in the array, but not the width of the vectors within the array.

You can also write functions to do remapping, though this can be suboptimal as the implementation tools may try to keep unrelated signals together as a bus. Lastly, you could do code generation to make new HDL files as needed (similar to coregen).
 
permute said:
Yes, and vhdl2008 also supports having types as generics. then UI can be std_logic/signed/unsigned/records/etc...
Click to expand...

VHDL 2008 does, but tools dont. But I do know that Quartus at least supports unbounded array types for both dimensions.
 
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