integer range conversion.???

me0414013 · Dec 4, 2013

inputs and signals:

Code:

sig_word :  in unsigned( 23  downto 0  );

signal sig_data : std_logic;

signal sig_counter : unsigned( 4  downto 0  );


 sig_data <= sig_word(to_integer(sig_counter) );

Iam getting the warning in the above line of the code.

---Index value(s) does not match array range, simulation mismatch.

since sig_word expects a range upto 23. but the to_integer is upto 31(since sig_counter is of 5 bits).

so how to specify the range(0 to 23) when i convert to integer??

aruipksni · Dec 4, 2013

me0414013 said:
inputs and signals:

Code:

sig_word : in unsigned( 23 downto 0 ); signal sig_data : std_logic; signal sig_counter : unsigned( 4 downto 0 ); sig_data <= sig_word(to_integer(sig_counter) );

Iam getting the warning in the above line of the code.

since sig_word expects a range upto 23. but the to_integer is upto 31(since sig_counter is of 5 bits).

so how to specify the range(0 to 23) when i convert to integer??

you can do your own "to_my_integer24" function, so only values from 0 to 23 will be returned....

TrickyDicky · Dec 4, 2013

Whats giving you the warning? A synthesisor will probably give you a 32:1 mux anyway, and just connect the extra inputs to 0 (even though they're not used).

I would never worry about a warning like this.. The simulation will throw an error if it does go above 23.

me0414013 · Jan 21, 2014

aruipksni said:
you can do your own "to_my_integer24" function, so only values from 0 to 23 will be returned....

Code:

function my_integer (constant A:unsigned (4 downto 0)) return integer is
variable B : integer range 0 to 23;
begin
B := to_integer(A);
return B;
end;

but again I am getting the same error while simulating... I want a memory depth of 24 only.. how would i ?

aruipksni · Jan 21, 2014

me0414013 said:
Code:

function my_integer (constant A:unsigned (4 downto 0)) return integer is variable B : integer range 0 to 23; begin B := to_integer(A); return B; end;

but again I am getting the same error while simulating... I want a memory depth of 24 only.. how would i ?

* you need to limit A range :

if ((A < 24) and (A>=0)) THEN
b := to_integer(a);
else
b := --here you decide what to do if out of range .....
end if;

* you can also use natural type instead of integer type, so number will start from 0.

* puting also assert, error sentance will give you more info about your problems...

TrickyDicky · Jan 21, 2014

This warning (and remember, it is only a warning, not an error) comes out from synthesis.
During synthesis, integer values need to be converted to binary. And binary values are always have a range 0 to 2^n. It doesnt matter whether you limit a return value to 23. The synthesised signal will always have n bits, giving a max value of 2^n-1. So the problem here is that you limited the memory to 24 elements, not the index size. The memory will probably also be expanded to 32 elements.

As long as the code never lets the index go above 23, you should be fine.

std_match · Jan 21, 2014

me0414013 said:
but again I am getting the same error while simulating... I want a memory depth of 24 only.. how would i ?

If you get the error when simulating, it means that your 5-bit unsigned had a value outside the range 0-23.
If you want simulation to match the real circuit, you must make sure that the 5-bit unsigned never gets a value outside the range 0-23.
Please show the code that updates the 5-bit unsigned. Is it a counter that wraps around from 23 to 0 ? How do you do that?

me0414013 · Jan 21, 2014

std_match said:
If you get the error when simulating, it means that your 5-bit unsigned had a value outside the range 0-23.
If you want simulation to match the real circuit, you must make sure that the 5-bit unsigned never gets a value outside the range 0-23.
Please show the code that updates the 5-bit unsigned. Is it a counter that wraps around from 23 to 0 ? How do you do that?

actually I am trying convert verilog code to vhdl...
and the module is instantiated by other modules..
while simulating verilog code its not showing any simulation error and the counter is going upto 100.
but when i converted the same module into vhdl then when the count value reach 87 simulation got stopped
the corresponding verilog code is

Code:

module coarsetiming(	clk,
										rst,
										valid_in,
										in_real,
										in_imag,
										valid_out,
										out_real,
										out_imag);
										
input clk;                          // Clock
input rst;                          // System reset
input valid_in;                     // Valid signal for input data
input signed [15:0] in_real;        // Real part of input data
input signed [15:0] in_imag;        // Imaginary part of input data
output reg valid_out;               // Valid signal for output data
output reg signed [15:0] out_real;  // Real part of output data
output reg signed [15:0] out_imag;  // Imaginary part of output data

// Variable Declarations
reg signed [15:0] RxBuffer_real[87:0];
reg signed [15:0] RxBuffer_imag[87:0];
reg [8:0] count;
reg [6:0] CorrCount;
reg [6:0] CorrIndex;
reg [38:0] CorrMagMax;

reg signed [19:0] Corrreal;
reg signed [19:0] Corrimag;

// Buffering the input samples for the next block
always @(`CLK_EDGE clk or `RESET_EDGE rst) begin	
	if (rst == `RESET_ON) begin
		out_real <= 0;
		out_imag <= 0;
	end
	else if (valid_in == 1) begin
		out_real <= in_real;
		out_imag <= in_imag;	
	end
end

wire [38:0] CorrMag;
assign CorrMag = Corrreal*Corrreal + Corrimag*Corrimag;

// Performing Synchronization
always @(`CLK_EDGE clk or `RESET_EDGE rst) begin	
	if (rst == `RESET_ON) begin
		count <= 0;
		CorrCount <= 0;
		Corrreal <= 0;
		Corrimag <= 0;
		CorrMagMax <= 0;
		CorrIndex <= 0;
		valid_out <= 0;
	end
	else if (valid_in == 1) begin
		if (count > 40 && CorrCount < 45) begin
			Corrreal <= RxBuffer_real[CorrCount] + RxBuffer_real[CorrCount+4] + RxBuffer_real[CorrCount+8] - RxBuffer_real[CorrCount+12] -  
                                          RxBuffer_real[CorrCount+16] - RxBuffer_real[CorrCount+20] + RxBuffer_real[CorrCount+24] - RxBuffer_real[CorrCount+28] -  
                                          RxBuffer_real[CorrCount+32] + RxBuffer_real[CorrCount+36] - RxBuffer_real[CorrCount+40];
			Corrimag <= RxBuffer_imag[CorrCount] + RxBuffer_imag[CorrCount+4] + RxBuffer_imag[CorrCount+8] - RxBuffer_imag[CorrCount+12] - 
                                            RxBuffer_imag[CorrCount+16] - RxBuffer_imag[CorrCount+20] + RxBuffer_imag[CorrCount+24] - RxBuffer_imag[CorrCount+28] - 
                                            RxBuffer_imag[CorrCount+32] + RxBuffer_imag[CorrCount+36] - RxBuffer_imag[CorrCount+40];			
			CorrCount <= CorrCount + 6'd1;
			if (CorrMag > CorrMagMax) begin
				CorrIndex <= CorrCount-6'd1;
				CorrMagMax <= CorrMag;
			end
			RxBuffer_real[count] <= in_real;
			RxBuffer_imag[count] <= in_imag;
			count <= count + 6'd1;
		end
		else if (count >= CorrIndex+88) begin
			valid_out <= 1;
		end
		else begin
			RxBuffer_real[count] <= in_real;
			RxBuffer_imag[count] <= in_imag;
			count <= count + 6'd1;		
		end
	end
	else begin
		valid_out <= 0;
	end
end


endmodule

and the converted vhdl module is

Code:

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
entity coarsetiming is 
     port (
        clk :  in std_logic;
        rst :  in std_logic;
        valid_in :  in std_logic;
        in_real :  in signed( 15  downto 0  );
        in_imag :  in signed( 15  downto 0  );
        valid_out :  out std_logic;
        out_real :  out signed( 15  downto 0  );
        out_imag :  out signed( 15  downto 0  )
    );
end entity; 


architecture rtl of coarsetiming is 
    type memory is array (0 to 87) of signed(15  downto 0);
    signal RxBuffer_real : memory;
    signal RxBuffer_imag : memory;
    signal count : unsigned( 8  downto 0  );
    signal CorrCount : unsigned( 6  downto 0  );
    signal CorrIndex : unsigned( 6  downto 0  );
    signal CorrMagMax : unsigned( 38  downto 0  );
    signal Corrreal : signed( 19  downto 0  );
    signal Corrimag : signed( 19  downto 0  );
    signal CorrMag : unsigned( 38  downto 0  );
    begin 
        process(rst,clk) 
        begin
           -- wait until ( ( rst'EVENT and ( rst = '1' )  )  or ( clk'EVENT and ( clk = '1' )  )  ) ;
            if ( ( rst = '1' )  ) then 
                out_real <= (others=>'0') ;
                out_imag <= (others=>'0') ;
            elsif ( clk'EVENT and ( clk = '1' )  )then 
                if ( ( valid_in = '1'  )  ) then 
                    out_real <= in_real;
                    out_imag <= in_imag;
                end if;
            end if;
        end process;
        CorrMag <= resize(unsigned( ( Corrreal * Corrreal )  + ( Corrimag * Corrimag )  ),39) ;
        process(rst,clk) 
        begin
            --wait until ( ( rst'EVENT and ( rst = '1' )  )  or ( clk'EVENT and ( clk = '1' )  )  ) ;
            if ( ( rst = '1' )  ) then 
                count <= (others=>'0') ;
                CorrCount <= (others=>'0') ;
                Corrreal <= (others=>'0') ;
                Corrimag <= (others=>'0') ;
                CorrMagMax <= (others=>'0') ;
                CorrIndex <= (others=>'0') ;
                valid_out <= '0' ;
            elsif ( clk'EVENT and ( clk = '1' )  )then 
                if ( ( valid_in = '1'  )  ) then 
                    if ( ( ( count > 40  )  and ( CorrCount < 45  )  )  ) then 
                        Corrreal <= resize(( ( ( ( ( ( ( ( ( ( RxBuffer_real(to_integer(CorrCount)) + RxBuffer_real(to_integer( CorrCount + 4  ) ) )  +
                                                                           RxBuffer_real(to_integer( CorrCount + 8  ) ) )  - RxBuffer_real(to_integer( CorrCount + 12  ) ) )  -
                                                                           RxBuffer_real(to_integer( CorrCount + 16  ) ) )  - RxBuffer_real(to_integer( CorrCount + 20  ) ) )  + 
                                                                           RxBuffer_real(to_integer( CorrCount + 24  ) ) )  - RxBuffer_real(to_integer( CorrCount + 28  ) ) )  - 
                                                                           RxBuffer_real(to_integer( CorrCount + 32  ) ) )  + RxBuffer_real(to_integer( CorrCount + 36  ) ) )  -
                                                                           RxBuffer_real(to_integer( CorrCount + 40  ) ) ),20) ;
                        Corrimag <= resize(( ( ( ( ( ( ( ( ( ( RxBuffer_imag(to_integer(CorrCount)) + RxBuffer_imag(to_integer( CorrCount + 4  ) ) )  +
                                                                            RxBuffer_imag(to_integer( CorrCount + 8  ) ) )  - RxBuffer_imag(to_integer( CorrCount + 12  ) ) )  - 
                                                                            RxBuffer_imag(to_integer( CorrCount + 16  ) ) )  - RxBuffer_imag(to_integer( CorrCount + 20  ) ) )  + 
                                                                            RxBuffer_imag(to_integer( CorrCount + 24  ) ) )  - RxBuffer_imag(to_integer( CorrCount + 28  ) ) )  - 
                                                                            RxBuffer_imag(to_integer( CorrCount + 32  ) ) )  + RxBuffer_imag(to_integer( CorrCount + 36  ) ) )  -
                                                                            RxBuffer_imag(to_integer( CorrCount + 40  ) ) ),20) ;
                        CorrCount <= ( CorrCount + 1  ) ;
                        if ( ( CorrMag > CorrMagMax )  ) then 
                            CorrIndex <= ( CorrCount - 1  ) ;
                            CorrMagMax <= CorrMag;
                        end if;
                        RxBuffer_real(to_integer(count)) <= in_real;
                        RxBuffer_imag(to_integer(count)) <= in_imag;
                        count <= ( count + 1  ) ;
                    else 
                        if ( ( count >= ( CorrIndex + 88  )  )  ) then 
                            valid_out <= '1' ;
                        else 
                            RxBuffer_real(to_integer(count)) <= in_real;
                            RxBuffer_imag(to_integer(count)) <= in_imag;
                            count <= ( count + 1  ) ;
                        end if;
                    end if;
                else 
                    valid_out <= '0' ;
                end if;
            end if;
        end process;
    end;

while synthesizing i got the fallowing warning

WARNING:Xst:3035 - Index value(s) does not match array range for signal <RxBuffer_real>, simulation mismatch.

while simulating when the count value reaches to 87 the simulation stops..
and this module is dependent on other modules(its been instantiated) . so i am unable to proceed further.

TrickyDicky · Jan 21, 2014

Thats because the memory array only goes up to 87, and the count value is going over this value. There is no mechanism to stop this happening.

Welcome to EDAboard.com

integer range conversion.???

me0414013

Junior Member level 3

aruipksni

Full Member level 6

me0414013

TrickyDicky

Advanced Member level 7

me0414013

me0414013

Junior Member level 3

aruipksni

Full Member level 6

me0414013

TrickyDicky

Advanced Member level 7

std_match

Advanced Member level 4

me0414013

Junior Member level 3

TrickyDicky

Advanced Member level 7

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Connect with us

Online statistics

Forum statistics