#### sangitacp93

##### Newbie

Hello all,

While doing behavioral simulation, there is an error which says '

All the vector length used here is 4(3 downto 0)

Two doubts:

1. The range says 0 to 2147483647 , but I am using only 0 to 15(2**4)

2. The value -3. Sine

Please do suggest if there is any more changes for this. I am generating sine value array.

Thank you.

While doing behavioral simulation, there is an error which says '

and[VRFC 10-1537] value -3 is out of target constraint range 0 to 2147483647 ["C:/Users/S/SineDDS/SineDDS.srcs/sources_1/new/Sine.vhd":57]

[XSIM 43-3321] Static elaboration of top level VHDL design unit dds_sine_tb in library work failed.

All the vector length used here is 4(3 downto 0)

Two doubts:

1. The range says 0 to 2147483647 , but I am using only 0 to 15(2**4)

2. The value -3. Sine

Please do suggest if there is any more changes for this. I am generating sine value array.

Thank you.

Code:

```
architecture rtl of dds_sine is
constant C_LUT_DEPTH : integer := 2**4;
constant C_LUT_BIT : integer := 4;
type t_lut_sin is array(0 to C_LUT_DEPTH-1) of std_logic_vector(C_LUT_BIT-1 downto 0);
-- generate sine value
function init_lut_sin return t_lut_sin is
variable v_sin_table : t_lut_sin:=(others=>(others=>'0'));
variable v_tstep : real :=0.0;
variable v_sine_sgn : std_logic_vector(C_LUT_BIT-1 downto 0):=(others=>'0');
constant c_step : real := 1.0/real(C_LUT_DEPTH);
begin
for index in 0 to C_LUT_DEPTH-1 loop
v_sine_sgn := std_logic_vector(to_unsigned(integer(round(2.0**(C_LUT_BIT-1)*sin(MATH_2_PI*v_tstep))),C_LUT_BIT)); --(sin (2PI/2^n)) --line:57
v_sin_table(index) := v_sine_sgn;
v_tstep := v_tstep + c_step;
end loop;
return v_sin_table;
end function init_lut_sin;
```

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