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[SOLVED] FPGA configuration failure: connection set

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Reissner

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Hi all,

I have a question on the consequences of a configuration error:
If a failure in configuration memory causes a connection to be set: what may happen?
Is it conceivable, that logic elements come into the game which should be passive?
So functionality is introduced which is nowhere specified?

Or are the unused LUTs programmed in a way, that they have no effect
even if they are connected by accident?
I asked because i have the impression that my config-file has constant length...


Thanks for discussing.

Ernst
 

I would expect there to be some CRC to prevent random bit flips burning down your board...
 
yes, i think so as well.
But if CRC does not recognize the problem,....

Are the un-used parts of the FPGA programmed in a safe manner - whatever this means?
 

Reissner said:
But if CRC does not recognize the problem,....
Click to expand...

Then you should have used your gift for finding unlikely branches in reality to buy a lottery ticket.


Translation: that is a rather unlikely scenario, and as such a wee bit of a waste of time IMO. Or if you think it's a problem, based on what MTBF calculation do you think that?
 
Last edited:
Or if you think it's a problem, based on what MTBF calculation do you think that?
Click to expand...
yes, thats what i fear.

Could you also say something responding my other sentence:
Are the un-used parts of the FPGA programmed in a safe manner - whatever this means?
Click to expand...
 

Reissner said:
yes, thats what i fear.

Could you also say something responding my other sentence:
Click to expand...

Actions based on uninformed fear? Are you from America? o_O Did you do a MTBF calculation showing the sense or nonsense of worrying about the joint probability of flipped bits && CRC hash collision resulting in releasing the magic smoke?

And yes, unconfigured logic will be in a boring not-going-to-blow-your-board-up state. Unused outputs will be high-Z. You can read all this and more fun details in the configuration guide for your chosen fpga.
 
Hei mrflibble :)
I like your humor :):)
And I like that unconfigured logic is indeed configured in boring 'Z-state'.
Ah, and I am not from the US... I am German.. so concerns are quite natural for me :).
 

Hey! I am American and it is my contention that we act from uninformed hubris and not uninformed fear. Back to topic. With Altera devices there is a CONF_DONE output which can be checked to verify the configuration was successful. I would think Xilinx has a similar signal. I often put this on a micro-controller input and check it. For one thing, any peripheral should check it to make sure the FPGA is done with configuration before trying to communicate with it. I agree 100% that the possibility of a corrupted configuration sequence happening and leading to improper functionality is very low. However, if possible, it does not hurt to check that configuration completed OK.
 
Ok, uninformed fear taking action to find information versus uninformed hybris acting uninformed.
Back to topic: As you said, I shall check the configuration manuals for some information that indeed Z is ensured for unused parts of fpga.
I think this was the valuable hint.

Then I shall close this thread because all is answered. Thanks to US.
 

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