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performance degrades a lot in extracted simulation

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prcken

prcken

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Hi,

I am doing the extracted simulation for the limiting RX, please refer to the attached document (schematic layout and plots) and help to think about what would cause this performance degradation?

fig3 is the AC magnitude response after TIA, Limiting amp, and output buffer, the results are got from individual extracted cells by using config in Cadence simulation.

fig4 is the same plot for the overall extracted simulation.

actually the metal connection between each blocks are not very long. any ideas about this?

thanks for your time!
 

Attachments

  • bugs.pdf
    228 KB · Views: 144

Hi,

Not only resistace but also the capacitance of the circuit affects the AC charecteristics of the Circuit..
Certainly, There is some degradation in your outputs after Layout extraction...
It cannot be eliminated fully...

You ensure that whether the output is meeting its specification or not...

If it meets specification.. you can finalise the circuit...

Thanks
 

prcken said:
actually the metal connection between each blocks are not very long. any ideas about this?
Click to expand...

I guess the shift of the lower pass band frequency limit from several MHz to several tens of MHz is your problem, isn't it?

If the connections between the blocks are responsible, you could check by artificial (manual) decrease or increase of their parasitics.
 

erikl said:
I guess the shift of the lower pass band frequency limit from several MHz to several tens of MHz is your problem, isn't it?
Click to expand...

yes, the overall frequency response should be a band pass like due to there is low-pass in the feedback system (DC offset cancellation), the lower cut-off frequency should be around MHz that can filter out the DC offset, or low-frequency noise.

- - - Updated - - -

kenambo said:
Hi,

You ensure that whether the output is meeting its specification or not...

If it meets specification.. you can finalise the circuit...

Thanks
Click to expand...

the output frequency response is not meeting the spec.
 

The low frequency gain rolloff is peculiar, as outcomes
from adding parasitic capacitance go. You'd expect
simple shunt loading to bother the high end.

I can't make out useful detail in the .pdf but recommend
you pick off more points along the lineup and see where,
more specifically, you're taking the hit. You should be
able to criticize block gain & phase individually and see
the most discrepant.
 

dick_freebird said:
The low frequency gain rolloff is peculiar, as outcomes
from adding parasitic capacitance go. You'd expect
simple shunt loading to bother the high end.

I can't make out useful detail in the .pdf but recommend
you pick off more points along the lineup and see where,
more specifically, you're taking the hit. You should be
able to criticize block gain & phase individually and see
the most discrepant.
Click to expand...

Thanks. today i did lots of small modification, and re-simulated (see the attached), I also increased the width of power supply metal, checked the critical DC operating point, especially the output of the feedback opamp, seems correct, could not find the root cause.
 

Attachments

  • bugs2.pdf
    394.9 KB · Views: 130
Last edited:

Hi,

Make your circuit meets your specification...
If not then make some changes in the layout

To find the root cause See where the output is deviating from the normal one and change according to that..
 

I tried different options (R+C+Cc, R+C, R, C+Cc, No R/C) in PEX, found out that the parasitic R extract caused this degradation. the simulation results of C+Cc and No R/C extraction work fine.
I was trying to figure out what would cause the parasitic R, by looking into the RVE of the PEX, I could see the R count and can trace down, but it is hard to find where caused this problem
I couldn't find a place the metal resistance will be potentially large in my layout.
any comments?
Thanks!
 

Attachments

  • extract.jpg
    extract.jpg
    13.5 KB · Views: 174
Last edited:

prcken said:
I couldn't find a place the metal resistance will be potentially large in my layout.
any comments?
Click to expand...

A w.c. value for a single contact/via connection instead of a required double contact/via connection?
 

erikl said:
A w.c. value for a single contact/via connection instead of a required double contact/via connection?
Click to expand...

for wires conducting current, i have more than two vias, for voltage wires, i have at least two vias.
yes, i found how to check/highlight the resistance on the metal, and i am making it wider.
 

Hi,

How is your length matching and device matching..

thanks
 

Dominik Przyborowski said:
Have You similar results for extracted cells from calibre and assura?
Click to expand...

no, i don't have the assura tool

- - - Updated - - -

kenambo said:
Hi,

How is your length matching and device matching..

thanks
Click to expand...

i have paid attention to the matching, i don't think that caused the post-simulation discrepancy. i suspect the current of the current mirror is changed. but i haven't checked it out so far.
 

I asking because I remember big difference of circuit performance between schematic, calibre pex extracted and assura extracted views. The assura extracted and schematic has similar performance while pex give me terrible results. After fabrication, the measurements shows results similar to assura extraction. Chip was designed in ibm cmos8rf pdk.

Calibre are not a cadence tool so it is possible that she don't extract properly your circuit.
 
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Dominik Przyborowski said:
I asking because I remember big difference of circuit performance between schematic, calibre pex extracted and assura extracted views. The assura extracted and schematic has similar performance while pex give me terrible results. After fabrication, the measurements shows results similar to assura extraction. Chip was designed in ibm cmos8rf pdk.

Calibre are not a cadence tool so it is possible that she don't extract properly your circuit.
Click to expand...

good to know that, thanks.
I am also using ibm cmos8rf process.
 

Hi,

In the older versions of Calibre (before 2005) the following issue is appeared: during the PEX Netlist Distributed (R+C,CC,...) extraction the parallel branches of conductor could be broken thus often making the resistive path falsely long (especially for supply/groung). It could cause the significant voltage drop. Please check if your rules (PEX Netlist Distributed command) does not contain NOLOOP keyword (or if you use older versions of Calibre check if your CAlibre extraction rules contain LOOP keyword).
 

sdedov said:
Hi,

In the older versions of Calibre (before 2005) the following issue is appeared: during the PEX Netlist Distributed (R+C,CC,...) extraction the parallel branches of conductor could be broken thus often making the resistive path falsely long (especially for supply/groung). It could cause the significant voltage drop. Please check if your rules (PEX Netlist Distributed command) does not contain NOLOOP keyword (or if you use older versions of Calibre check if your CAlibre extraction rules contain LOOP keyword).
Click to expand...

Hi, I am using Calibre 2010, I checked run set rule (same as PEX Netlist Distributed command?) doesn't contain the NOLOOP. but, there is a LOOP in it like below
Capture.PNG
the code seems not make much sense, does it matter?
Thanks
 

The code in the picture doesn't make sense because it is part of the encrypted rules provided by the foundry; you would need to ask the foundry what the parasitic rules are doing. They might not be willing to provide much detail, but maybe they'll know of a problem with earlier PDKs and have an update for you.
 
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Hi,
encrypted rule file is an issue... I'm afraid that there is no other way for you than to check extracted netlist manually. First check if the netlist contains "noconn_..." net names - sometimes Calibre "cut" nets during R extraction. Second, try to use output netlist reduction (Tacer for ex.) and look for large resistance in unexpected place.
 
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