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About Standard Cell Libraries

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mehboobali

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Standard Cell Libraries in ASIC flow

Why the Standard cell Libraries (.lib) is used in ASIC flow. What happens if we dont use it....
Other than providing .lib in ASIC flow are there any other things which we can give input rather than .lib.?
The .lib process goes this way
Layout-->GDSII-->CDL(netlist)-->Spice extraction-->.lib-->db-->views

Why .lib is used in ASIC flow....??
 

Hi,

Lets think you didn't gave .lib in ASIC flow. How to know functionality of cell or cell delays or transition time or internal power for each cell.
.lib contains cell delays , functionality and power information.
In fab they will run different spice simulations and prepare .lib files.
 

Just a followup question which has interested me in a long time. Can anyone confirm if the .lib files from foundries are based on simulations or measurements ?
 

They are simulation based. The stdcell .lib has thousands of std cells and measuring them to create a model is not realistic.
 
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