[SOLVED] Spartan 3E Starter Kit Board - PROM Problem

Hello all,
Problem is , when trying to download my verilog code to platform flash prom (of xilinx ) the program (ISE Design suite)

said that the programming is done and all is okey, like this picture



on Master Serial mode .

now i should look at my kit and find that the done led lights (as usual ) but it's NOT !!
meaning that the fpga has not been programmed so what's the solution for this problem??

and just to know, it's not my first time to program the fpga using Master Serial mode

after that problem, i tried to program the fpga directly using JTAG mode and it works

but i still want to solve the problem of programming using platform prom

any ideas??
Thanks in advance.

MAAASD said:

Hello all,
Problem is , when trying to download my verilog code to platform flash prom (of xilinx ) the program (ISE Design suite)

said that the programming is done and all is okey, like this picture

View attachment 95030

on Master Serial mode .

now i should look at my kit and find that the done led lights (as usual ) but it's NOT !!
meaning that the fpga has not been programmed so what's the solution for this problem??

and just to know, it's not my first time to program the fpga using Master Serial mode

after that problem, i tried to program the fpga directly using JTAG mode and it works

but i still want to solve the problem of programming using platform prom

any ideas??
Thanks in advance.

Click to expand...

1./you might have hardware problem.
2./did it work with other bit files (reference bit files)?
3./ Did you select CCLK as the startup clock when generating your BIT file?
4./ ofcourse mode pins setting should be checked as well.

i've tried another file and same problem occurs

MAAASD said:

i've tried another file and same problem occurs

Click to expand...

mabee your problem is with the cpld device ?
mabee you should try to re-program it with default xilinx version.

Finally i've found the solution to this problem!
on this topic
https://www.edaboard.com/threads/104093/
check this post

snake68 said:

You are right about the problem! I think if a programming procejure (in iMPACT) fails, the original CPLD design will be deleted. So I downloaded the Default Xilinx CPLD Design file from **broken link removed** and programmed it into my board's CPLD. Fortunately it worked without errors and now my PROM works fine when I press the PROG button.
About programming the CPLD: iMPACT -> Boundary Scan -> xc2c64a -> Assign New Configuration File... -> original_CPLD_design.jed -> Program.

Click to expand...

i've tried it and it works like a charm!
Thanks a million.