Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Power-gating is one of the most effective standby-leakage reduction technical recently developed. In a power gating design, sleep transistor(ST) are used as switches to shut off power supplies of the standby circuits, as shown in fig. 1. A ST is referred to either a PMOS or NMOS high Vth transistor that connects permanent power supply to circuit power supply which is commonly called “virtual power supply”. The PMOS ST is used to switch VDD supply and is hence called “header switch”. The NMOS ST controls VSS supply can hence is named “footer switch”. In sub-90nm designs, either header or footer switch is only used due to the constraints of sub-1V power supply voltage and area penalty of the STs
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
