Device sizing for input stage of R-R comparator/opamp

Hello, I'm currently doing my first "real" cmos design for fabrication (0.5um 5V onsemi). One of the main building blocks of my project is a rail-rail high speed comparator. I've done some rough simulations using a typical complementary input stage, and I find that it does work rail to rail, but the gain and speed are significantly reduced when Vcm is biased towards either supply (not just due to gm doubling at midpoint). When looking closely at the simulations, it seems that this is because some transistors are falling out of saturation (but not cutting off).

Rather than just randomly change sizes hoping for a working solution, I'm trying to approach this with some basic theory, but I'm not getting agreeable results so far. Here's a simplified circuit approximating the behavior of one half of a diff pair with active load. I sweep the input (V2) DC bias and look at the M1 and M2 operating conditions to see whether they are in saturation:


On paper I worked out that for M1 and M2 to both stay in saturation, I have to meet the following condition (I'm only interested in the low common mode input range limit for the P input stage):
Vin_min=Vgs_M2-Vdss_M2+Vdss_M1, which reduces to
Vin_min=Vtp-√(2*Ib/βp)+√(2*Ib/βp)+√(2*Ib/βn), which again reduces to
Vin_min=Vtp+√(2*Ib/βn)

So I notice that is completely independent on the sizing of M2, and the Vth of M1. When I run the simulation though, I find that M2 drops out of saturation at higher than expected input voltages, and the biasing conditions don't match up very well with the basic equations I'm familiar with. At first I thought it might be body effect on M2, but if anything shouldn't that improve my input range by making Vtp larger (more negative)?

Is my approach just oversimplified, or maybe there's something wrong with my simulation? Any advice would be appreciated.

mtwieg said:

Here's a simplified circuit approximating the behavior of one half of a diff pair with active load.

Click to expand...

Okay, I don't know how representative this schematic is of your actual circuit—just how much it has been simplified—but the schematic you've shown violates a rule in IC design: Don't make dueling current sources! (unless you want one of them to transition into triode).

See this link.

Right, that's certainly not how the real circuit is configured. in reality M1 (and all the other loads on the diff pair) is configured as a MOS diode which drives another current mirror to the next stage. I just want to know if my analytical approach is correct.

Also when doing hand calculations of operation, I've been referring to the model parameters I'm using, but there's a lot of ambiguity in here... there are several apparent values given for threshold voltage, but I don't see any number given for surface potential, which would be necessary for determining the body effect.

mtwieg said:

Right, that's certainly not how the real circuit is configured. in reality M1 (and all the other loads on the diff pair) is configured as a MOS diode which drives another current mirror to the next stage.

Click to expand...

Okay, that explains things. With M1 diode-connected, it will always be in saturation (as long as it has current) with a voltage of Vtn+Vsatn (where Vsatn=√(2*Ib/βn); depending on sizing, this might be 50mV to 500mV ). For M2 to stay in triode, M2's Vsd must be greater than its saturation voltage (Vsd>Vsatp=√(2*Ib/βp) ). Since M2's Vsd is Vin+Vtp+Vsatp-Vtn-Vsatn (KVL), we have the condition: Vin+Vtp+Vsatp-Vtn-Vsatn > Vsatp. This means Vin+Vtp-Vtn-Vsatn > 0, or Vin>Vtn+Vsatn-Vtp. Assuming Vtn=Vtp, we must satisfy Vin>Vsatn. In reality, the body effect will cause Vtp to increase—and this helps you by allowing Vin to go lower, maybe an additional 300mV. But since Vtp and Vtn are subject to change over process corners, I wouldn't rely on this always giving the CMIR you want.

You should use a folded cascode structure. This would look similar to the structure you have above where M1 is not diode-connected. Instead, the point where M1 and M2 meet is turned into a low-impedance node by a common-gate stage (a "folded cascode" transistor), and the difference in current is sent through the source of this new cascode MOSFET. Bias the cascode FET such that M1 is just barely kept in saturation (with a small margin). If it was just perfect (so that M1's Vds is equal to Vsatn), then the Vin CM range becomes bigger by one NMOS threshold voltage: Vin>Vsatn-Vtp. This can easily exceed the rail.

Check out this book by Hans Camenzind, page 8-9 (119 in normal page numbering systems). There are several variations on the theme of making folded cascodes; he has chosen the approach where the cascodes are biased such that the mirror load (M1 in your case) is in triode. This is okay too, but matching becomes a greater concern and overall Gm is somewhat reduced.

Thanks for the reply Zeker

I'm familiar with the folded cascode, and I'm able to simulate it well with just a single input diff pair, but not when moving to a complementary input. For some reason, summing the outputs of the two complementary cascode stages severely imacts gain... Also I wanted to have some built in hysteresis, and I'm unsure of how to implement that with a cascode structure.

For example here's some nice results I get with a single ended cascode stage. Plots show the differential output vs input with different Vcm.



Now I try a complementary input with the currents summed directly:


So the gain is far lower. The one trace which looks normal is for Vcm=2.5V. When Vcm is away from the midpoint, the outputs are pinned near their limits, meaning that the pairs M9/M10 or M10/M11 are not in saturation. So I'm assuming this is due to some biasing offset or gain mismatch between the complementary inputs, but I don't know how to deal with it.

It's not exactly clear what you want to achieve. The circuit looks like a fully differential amplifier without the necessary common mode feedback.

That would just be the front end of the comparator, I'd also want hysteresis and then a totem pole output stage. I have the outputs labeled as if it were differential, but it shouldn't actually function like that. In the first version the + output is pinned to a constant bias voltage. In my second circuit I see your point, it would basically be diff out. But I think that's my problem, I don't know how to sum the two paths together properly.

Edit: figure 8-22 of the document ZekeR posted shows a complementary input with cascode, and they seem to sum the currents directly like I'm trying to do... the big difference is that they are using a mirror for the upper part of the cascode, while I'm using externally biased current sources... perhaps that's necessary to make things balance out?

double edit: yes, changing one of the cascode stages from sources to mirrors seemed to do the trick. Now, what is a convenient way to integrate hysteresis into that topology in a way such that the hysteresis is reasonably constant vs Vcm?

mtwieg said:

Now, what is a convenient way to integrate hysteresis into that topology in a way such that the hysteresis is reasonably constant vs Vcm?

Click to expand...

Normally, a comparator will provide sufficient gain so that its output is at logic levels. Said logic level signal can be used to turn on or off current sources, attach or detach resistors, or enable/disable extra diffpair inputs in order to add balance or imbalance to the comparator—and this will reflect at the input as a [purposefully added] offset voltage. Getting a perfectly reproducible voltage hysteresis might be tricky (well, there are various techniques depending on what you're looking for), but if you're okay with just a hand-wavy, "approx. xxx" hysteresis then it's a no-brainer. I'd probably enable/disable an extra current leg at the current summing stage—this would make an offset voltage which depends on the input stage's gm, and therefore changes 2x when the gm doubles. For lots of things, this is good enough.

I suppose I liked the cross-coupled-latch circuit because its feedback follows a very compact path, and is pretty much immune to instability. Using feedback from the full swing output could work in principle, but I'm afraid of parasitic oscillations occurring, since my hysteresis gap won't be very large.

There are tricks that can be played; specifically, you should ensure the input hysteresis always latches before the output toggles—in both directions. You can also give your comparator an "AC Kick" which, upon reaching threshold, kicks the input beyond the threshold.

mtwieg said:

Hello, I'm currently doing my first "real" cmos design for fabrication (0.5um 5V onsemi). .

Click to expand...

Hello, I am sorry that I have no answer for your post.. but I am interesting on the technology you are working with, Are you getting it from MOSIS by using MEP account ??? and please I also would like to know which kind of EDA you are using ?

Thank you

So I thought I had a cascoded design working well, but it turned out I wasn't biasing things correctly and some transistors were in triode region... even so the simulation results looked good enough in LTspice, but then I recreated it in cadence and got much slower response with Vcm near the supply rails (like 20ns in cadence vs 5ns in LTspice). Not sure why the difference in simulations was so large, my model parameters should be the same...

I think for now I'm going to stick to the design using self-biased current mirrors as the loads for the input diff pair. That means my input range is not optimal, but cadence says it will be fast enough over my expected range... even so I'd like to investigate the matter more deeply. I still haven't seen an example of a r-r comparator input stage using folded cascodes. The part that still gets me is how the currents are summed.

Junus2012 said:

Hello, I am sorry that I have no answer for your post.. but I am interesting on the technology you are working with, Are you getting it from MOSIS by using MEP account ??? and please I also would like to know which kind of EDA you are using ?

Thank you

Click to expand...

Yeah, I believe it's an MEP run from my school. For this, I'm using Cadence 5.1.

mtwieg said:

Yeah, I believe it's an MEP run from my school. For this, I'm using Cadence 5.1.

Click to expand...

Dear mtweig

Thank you for your response.
Actually I am also trying to create an account in MOSIS using MOSIS MEP instructional programme. But my actual problem that I dont have Cadence simulator. I only have OrCad.
I am trying to get Cadence but I came to know it is very expensive, could you tell me please how can get it for less price for the use of educational purpose ???

Thank you once again

mtwieg said:

So I thought I had a cascoded design working well, but it turned out I wasn't biasing things correctly and some transistors were in triode region...

Click to expand...

The way it is in Post#5, the input stage should still go into triode. The problem is that your cascode devices are sitting at too high of a voltage. This is because their source voltage, rather than being Vsat, is actually Vgs (e.g., M16's gate voltage is M16's Vgs + M15's Vgs. You'd prefer if M16's gate voltage was M16's Vgs + Vsat, so that when the gate voltage is fed to a cascode device like M9 or M10, their source voltage [which is a Vgs down] would be Vsat).

**broken link removed**--see page 4. There are other approaches too, depending on your needs. In Hans Camenzind's book, he shows several methods--see chapter 3.

mtwieg said:

Not sure why the difference in simulations was so large, my model parameters should be the same...

Click to expand...

Assuming the models were identical, they should get similar results. One possibility is that the model library was relying on some parameters that Cadence calculates. Note that when drawing a schematic in Cadence, some model parameters might be calculated using the built-in scripting language (Skill) and not actually included in the SPICE library--it's up to the foundry whether they wanted to make their models work that way.

As an aside, I whole-heartedly recommend reading through Hans Camenzind's (RIP) book. I bought the hardback for a whopping $20. The downside of the hardback is that it's in black-and-white, but I'm and old-fashioned kind of guy who prefers a book in physical form. His book is extremely helpful for building your intuition for IC design.