[SOLVED] Clarification on clock domain synchronization

I have a doubt here:



Here clkb samples DA, resulting in DB. DB2 is derived from DB which is metastable in 2nd cycle of clkb. So how we get clear levels at DB2 ? I mean how DB2 rises and falls on 3rd and 4th rising edge of clkb when DB itself is not clear(DB2 can be all time low also)?

I agree that the explanation is not good.

But here is the thing. Even though first FF has gone metastable, second FF will not be metastable even if the latched value is incorrect. In other words, due to metastability at the first FF, the value latched by second FF can be incorrect (50 % chance of it being incorrect due to metastability and 50 % chance of being correct again due to metastability).

Look for clock domain crossing threads on this website. There are very good discussions on this that will make you understand

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Look at this

http://www.eetimes.com/design/eda-design/4018520/Understanding-Clock-Domain-Crossing-Issues

The point is that "the logic value of DB2 maybe incorrect but won't be metastability"
When the first FF got metastable, the value will push to 1 or pull to 0 "finally after a clock period"
Therefore, the second FF will sample the intact voltage no matter it's true or wrong.

Usually, this type of synchronizer is used to sample the value which maintains longer.
For example, DA remains at least 2-3 cycles to guarantee the correctly sample.

"the logic value of DB2 maybe incorrect but won't be metastability"

well expained~

YuLongHuang said:

"the logic value of DB2 maybe incorrect but won't be metastability"

Click to expand...

Yeah that i understood, but how does it serve the purpose of signal integration? I mean DB2 may or may not have same but delayed pulses as DA always.
If this solution is something not completely full proof, then i got the answer.

babaduredi said:

Yeah that i understood, but how does it serve the purpose of signal integration? I mean DB2 may or may not have same but delayed pulses as DA always.
If this solution is something not completely full proof, then i got the answer.

Click to expand...

That is why the receiver side has to discard the value received in the first few (1-2 cycles) cycles to receive the correct value.

Does that make sense?

babaduredi said:

I have a doubt here:

Click to expand...

This is a terrible example...

The CLKA is toggling at a higher frequency than CLKB, trying to sample a pulse that doesn't span at least 1 clock cycle of the capture clock (CLKB) is prone to missing the pulse completely. As was mentioned in another post sending a pulse is usually done with something that is more like 2-3 clocks wide in the capture clock domain.

ads_ee said:

The CLKA is toggling at a higher frequency than CLKB, trying to sample a pulse that doesn't span at least 1 clock cycle of the capture clock (CLKB) is prone to missing the pulse completely. As was mentioned in another post sending a pulse is usually done with something that is more like 2-3 clocks wide in the capture clock domain.

Click to expand...

This is somewhat i was expecting. Thanks YuLongHuang and ads_ee. So now the problem reduces to: this 2 flop sync or 3 flop sync is good synchronization technique when signal is stable for at least 2-3 time period of capture clock. So now if we take normal FIFO example where writing is faster than reading than even with grey coded pointers, is it sure that wptr synchronized in read clock domain will be correct in all the cases?