[SOLVED] SmartFusion Eval Board JTAG problem

I recently purchased a SmartFusion Eval Kit for home use, to supplement my work setup (SmartFusion Dev Kit). When trying to program the Eval Board with a sample project, I get errors as seen here:
'C:\Microsemiprj\SC_standalone\polled_uart\UART\designer\impl1\UART_MSS_fp\UART_MSS.pdb' has
been loaded successfully.
DESIGN : ; CHECKSUM : 0000; PDB_VERSION : 1.7
The 'update_programming_file' command succeeded.
The 'set_programming_action' command succeeded.
programmer '77850' : Scan Chain...
Warning: programmer '77850' : Vpump has been selected on programmer AND an externally provided
Vpump has also been detected. Using externally provided Vpump voltage source.
Error: programmer '77850' : Signal Integrity Failure
Integrity Check Pattern Not Found.
Integrity Check Pattern :
550FAAF000FF0000FFFF
IrScan Error.
TDO stuck at 0
Chain Analysis Failed.
Error: programmer '77850' : Data Bit length : 8272
Error: programmer '77850' : Compare Data :
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\

I've rechecked the jumper settings and everything seems fine. Has anyone seen something like this (assuming no actual hardware issue like TDO being shorted to ground)? I haven't encountered this with the Dev Kit, using the LCPS.

Silly question, but are you providing power from the serial port as well? You do need both ports connected as the JTAG port does not provide power to the FPGA

Thanks, but yes, had them both connected. It was an issue with the jumpers (the silk screen on the board wasn't clear as to the pin orientation of some of the 3-pin jumpers). However, now after using the board for a few weeks, it is back to this condition, coincidental with programming the device. I am no longer able to use the softconsole debugger or use FlashPro to reset the M3. Any thoughts? Is it possible to kill the JTAG interface by programming the device?

chipseller said:

Silly question, but are you providing power from the serial port as well? You do need both ports connected as the JTAG port does not provide power to the FPGA

Click to expand...

Assuming that JP7 and 10 are in the correct positions (pins 1 - 2 closed) I can only think that this must still be a power related issue. As you are using Softconsole to debug these jumpers should not need to be changed. I don't know which variant of the board you are using, the one shown on the web is quite a bit different to mine, but on the latest version these positions are to the right if the i/o connector is at the bottom. Otherwise is still sounds like a USB Power supply issue. The JTAG pins are dedicated function, so you cannot disable the jtag functionality by programming the FPGA and the only part of the device which can be program protected is the flash memory, but that woukld not affect the chain integrity. Another option is to set the VPRSM jumper to external supply (pins 2 - 3). If this is set to internal (which it seems to be by default) and you have not implemeted the VPRSM in your design then there will be no 1.5V to power the FPGA. I can't think of anything else.

Thanks, chipseller! Oddly enough, the VRPSM jumper (J6) was already in the external position. However, moving it to internal seemed to make it work. Then returned it to external position and it still works!

Thanks, much!

chipseller said:

Assuming that JP7 and 10 are in the correct positions (pins 1 - 2 closed) I can only think that this must still be a power related issue. As you are using Softconsole to debug these jumpers should not need to be changed. I don't know which variant of the board you are using, the one shown on the web is quite a bit different to mine, but on the latest version these positions are to the right if the i/o connector is at the bottom. Otherwise is still sounds like a USB Power supply issue. The JTAG pins are dedicated function, so you cannot disable the jtag functionality by programming the FPGA and the only part of the device which can be program protected is the flash memory, but that woukld not affect the chain integrity. Another option is to set the VPRSM jumper to external supply (pins 2 - 3). If this is set to internal (which it seems to be by default) and you have not implemeted the VPRSM in your design then there will be no 1.5V to power the FPGA. I can't think of anything else.

Click to expand...