Stablizing Ldmos with K <1

hi,

ADS Software model of SD57060 shows that the device is unstable at 945MHz. To get stability factor greater than one over the desired band , i add 3 ohm resistor at the gate side. After stabilizing it load pull test shows that maximum power can not be achieved using 3 watt input power as shown in the device datasheet. Why datasheet shows maximum power without stabilizing the device

Well, since the input impedance of that device is 0.7 ohms, adding a 3 ohm series resistor at the gate will have a very big impact! Try stabilizing it using some other method. The data sheet shows a recommended circuit layout.

thanks for reply.

what are other stabilizing methods?

Since u interested at PA, so u have a few options: series resistor at gate (like u did), Feedback D-G, Adding shunt RLC to GND at gate, bias

Re: Stablizing Ldmos with K &lt;1

thanks for reply.

Simulation of sd57060 exactly with the layout given in the datasheet Shows k>1 .

ADS shows the following warning. even at low drive power 25dbm

Simulation / Synthesis Messages

Warning detected by hpeesofsim during HB analysis `HB1'.
Circuit converged with at least one device's P-N junction current
exceeding the explosion current and junction has been linearized.
You may want to increase the explosion current in the device model or in
the Options (if the parameter is not given in the model) and resimulate.
You may need to increase Maximum number of warnings under Output tab
in Options to see which devices have been linearized.
Warning detected by hpeesofsim during HB analysis `HB1'.
Diode `X1.DIODE1' explosion current exceeded.

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what is the configuration for RLC at gate to source?

Re: Stablizing Ldmos with K &lt;1

adnan012 said:

what is the configuration for RLC at gate to source?

Click to expand...

Resistor inductor and Capacitor (from gate to gnd) generally i used with this as band stop filter to reject low freq, for example 100MHz

hi

Is it possible to stabilize amplifier by fixing only input and output matching networks? I noticed that during the adjustment of input and output matching networks, the ADS SIMULATION shows that SD57060 becomes marginally stable over certain bandwidth.

Yep why not...

what is the proper method of stabilizing LDMOS. Should i use gate resistor along with matching network.