ranjbar_7
Junior Member level 1
hi
in the scipt that we wrote for design compiler what we should write for geting delay report?
i have written this script what should I add to it?
--------------------------------------------------------
set my_files second.vhd
set my_toplevel project1
set my_clock_pin CLK
set my_clk_freq_MHz 100
set my_input_delay_ns 0
set my_output_delay_ns 0
set link_library ./osu025_stdcells.db
set target_library ./osu025_stdcells.db
define_design_lib WORK -path ./WORK
set_ultra_optimization true
set_ultra_optimization -force
analyze -f verilog $my_files
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify
set my_period [expr 1000 / $my_clk_freq_MHz]
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock !=
in the scipt that we wrote for design compiler what we should write for geting delay report?
i have written this script what should I add to it?
--------------------------------------------------------
set my_files second.vhd
set my_toplevel project1
set my_clock_pin CLK
set my_clk_freq_MHz 100
set my_input_delay_ns 0
set my_output_delay_ns 0
set link_library ./osu025_stdcells.db
set target_library ./osu025_stdcells.db
define_design_lib WORK -path ./WORK
set_ultra_optimization true
set_ultra_optimization -force
analyze -f verilog $my_files
elaborate $my_toplevel
current_design $my_toplevel
link
uniquify
set my_period [expr 1000 / $my_clk_freq_MHz]
set find_clock [ find port [list $my_clock_pin] ]
if { $find_clock !=
- } {
set clk_name $my_clock_pin
create_clock -period $my_period $clk_name
} else {
set clk_name vclk
create_clock -period $my_period -name $clk_name
}
set_driving_cell -lib_cell INVX8 [all_inputs]
set_input_delay $my_input_delay_ns [all_inputs]
set_output_delay $my_output_delay_ns [all_outputs]
compile -ungroup_all -map_effort medium
compile -incremental_mapping -map_effort medium
check_design
report_timing
report_timing -delay min
report_timing -delay max
write -f ddc -o ./Reports/myddc.ddc
write -f verilog -o ./Reports/netlist_verilog.v
write -f vhdl -o ./Reports/netlist_vhdl.vhdl
write_sdf ./Reports/Stndrd_Dly_Frmt.sdf
write_parasitics -o ./Reports/C_R_delays.spef
write_sdc ./Reports/sdc.sdc