Simple verilog code for FPGA

I need a mips verilog code that is simple , educational, based on data path , tested and works on FPGA.
I'm working on Altera DE2 115.
I need the code to read from a file the instructions and writes the solution back to a file.

Can I have a code with all these options ?
I found codes for processors in open-cores but I can't differentiate and get the best one and matches my needs, I need some help to get a code that is simple and at the same time I can ensure that it will work.

for Example in this link
https://opencores.org/projects

there are several codes some of them have status new and some done , does it mean that done is better ? can you hepl me how to get a suitable code?

In the past I used the MIPS789 Verilog model from OpenCores, available at the following link

https://opencores.org/project,mips789

It is quite simple, based on a 5-stages pipeline model and it has been shown to work on FPGA devices.

Cheers

Thank you very much , does it read and write from a file ??

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Thank you very much , does it read and write from a file ??

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Thank you , it's very helpful ,I downloaded the folder from this resource ,Can you tell me hints about which files to use ?as I'm very confused and haven't tried verilog before .

as I'm very confused and haven't tried verilog before .

Click to expand...

In that case a good verilog book + some online tutorials seem to be in order.

This one's is always nice: https://www.asic-world.com/verilog/veritut.html

Random other links:

https://www.fpga4fun.com/

https://www.amazon.com/s/ref=nb_sb_noss_1?url=search-alias=aps&field-keywords=verilog+primer

The release version does not have any read/write from/to file capabilities. However, it is very easy to do so using tasks $fread, $fwrite, etc... You can find good tutorials on the net (and on the links suggested by 'mrflibble').

The first suggestion from 'mrflibble' is a "classical" one to get start with. However, let me suggest you to first get the very basics from Verilog (e.g., using the links provided above), and then dig your hands down into experimentation with the code and, above all, the tools! Once you start going through simulation you will go through real HDL learning! At least, this is what I think and how I approached the whole thing ;-)

Cheers

Regarding tools, I'd suggest getting the toolchain from either Altera or Xilinx. Doesn't matter so much which for learning purposes I'd think. That way you get your hands on some real tools with a trial license. Why those two as suggestion? Because those have a fairly high user base, so in case of WTF you can 1) google 2) google more 3) use a forum, where 4) they tell you to google you lazy b*stard! Case in point, personally I use ISE (from Xilinx) and most errors and other weirdness I encounter I can fix myself just by doing steps 1 + 2, precisely because of the large user base.

And the plus of using a synthesis capable tool vs just simulation is that you can also make a few simple circuits, and see how they are synthesized. As in, you can see what kind of hardware your verilog code will produce. When stay in SimulationOnlyCountry for too long, you run the risk of learning bad habits. Bad habits such as writing code intented for hardware, but that cannot be synthesized.

I totally agree with 'mrflibble': I remember what an emotion once I synthesized the first design on a Xilinx FPGA and saw the whole thing on FPGA-Editor
I also suggest trying to understand the entire design flow, from RTL design down to place&route: I used to go through the entire flow by hand, using command-line to know exactly what I was doing. You learn a lot, really a lot.

Cheers