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constraining a design from scratch.

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vijay.mani884

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Hello all,

Kindly help me out.

Question1 : How to constraint a design from scratch, well i have a design running at 20ns (time period) . Now i have to constraint the design. I have to write a defaults.con for it.

Need advice.

In this. How can i model , uncertainty? How can i model inout and output delays? how to provide default drive strengths like "set_drive" and "set_driving_cell" commands.


Please advice. the only data available to me is the clock period i.e 20ns.

Awating a response.

Thanks
 

vijay,

Pls refer to synopsis design constraints and timing constraints user guide for more info... It explains each individual question of yours

But to answer your question how to constrain design below mentioned are some set of commands familiarly used. Even I missed out some commands but as per our requirement we keep those.

- Operating conditions
set_operating_conditions
- Wire load models
set_wire_load_mode
set_wire_load_model
- System interface
set_drive
set_driving_cell
set_fanout_load
set_input_transition
set_load
- Design rule constraints
set_max_capacitance
set_min_capacitance
set_max_fanout
set_max_transition
- Timing constraints
create_clock
create_generated_clock
group_path
set_clock_groups
set_clock_latency
set_clock_transition
set_clock_uncertainty
set_input_delay
set_output_delay

- Timing exceptions
set_false_path
set_max_delay
set_min_delay
set_multicycle_path
 

Hello Thanks for the quick reply,


I know how to specify the constraints, the commands and its usage. But my question is i wanted to know the factors which involves in defining the constraints.

Like for example,

if we are specifying uncertainty.

we will use this set_clock_uncertainty 5 [get_clocks CLK] now my questions is how do we take/decide this value "5". How do we model this? what are factors involved?

who will provide me this data? if we can approximate it then how do we do this?

Thanks again
 

In general all these data provide by the specification team. Based on this front end synthesis team develop constraints. And back end designers run with those constraints and provide feed back to them. It's a continuous loop. Definitely constraints defining is not a single shot.

For explanation I am considering your example itself, uncertainty is nothing but skew. skew wont observed during the logical synthesis stage. logically all flops need to get the clock at the same time but physically that's not possible. So, In logical synthesis stage itself they try keep uncertainty value so as to get the correct picture. Keeping tighter constraints at the logical stage becomes easy in terms of fix-ability at the physical stage. Let say 100ps be the target skew that observed during the physical design stage, at logical design stage constrain it for 150ps.
 

Thanks for the explaination. I agree to you, i still feel that there has to be some means to approximate the same. according to whatever you have told me i agree to it. Thats why i wrote in my first post that. I am have to constraint a design from scratch with only clock period in hand.I am trying to figure out the dependencies of these (timing) constraints. Because usually, what we do is we refer to the previous designs and try to keep tighter constraints and then try to meet the timings. But, think about it, if you have to a design which u need to constraint without any prior/other specs then how do we do it. well, thanks for your replies.
 

I agree with what bschaitanya posted. This is possibly the best explanation for your question.

Vijay - "But, think about it, if you have to a design which u need to constraint without any prior/other specs then how do we do it"

Based on your last post, it looks like you have started recently. In the academic world they don't tell you everything. In the real work environment it is simply impossible to start a design without any spec.
There are several large engineering departments involved in building a chip. The systems engineer will usually put a certain basic spec req. Then the circuit guys will give process related specs. Then Logic design engineers will take care of design related specs. + the test engineers will have their set of specs for test mode. All these specs put together will form the basis for constraints.

To answer your question - We simply cannot build a chip without any prior spec. It would be the dumbest thing to try in the real world.

If you have only clock period in hand and if you are working in a company, Then ask your boss or the system engineer to give the spec. You can start with the system engineer and then discuss with the rest.
If you are a student then you can simply assume any value for clock uncertainty, jitter etc to get timing closure and finish your project. You can assume a drive strength of BUF4 for Input ports and a output load of 200fF as a starting point. There is not a lot of theory behind these values.
 
i agree, Then how will the concept of "time budgeting" and "Load budgeting" comes into the picture? Are they related to specs?
 

"time budgeting" - It is a methodology by which you decide how your share a clock period between top level logic and block internal logic for interface paths. Lets say you have a clk period of 5ns. Your top level wants to use 3ns, so that means your block internal logic should fit within 2ns (assuming 0 uncertainty for simplicity). It is not related to spec. It is based on your knowledge of the design.

I am not sure what load budgeting means.
 

load budgeting is more related to fanout distribution (block to top interface), something like how many a output drive buffer can handle interface connected loads, and what min driving can be assumed for inputs
 

whats the percentage? can you throw some light on this? how do we assume that?
 

matter said:
I agree with what bschaitanya posted. This is possibly the best explanation for your question.

Vijay - "But, think about it, if you have to a design which u need to constraint without any prior/other specs then how do we do it"

Based on your last post, it looks like you have started recently. In the academic world they don't tell you everything. In the real work environment it is simply impossible to start a design without any spec.
There are several large engineering departments involved in building a chip. The systems engineer will usually put a certain basic spec req. Then the circuit guys will give process related specs. Then Logic design engineers will take care of design related specs. + the test engineers will have their set of specs for test mode. All these specs put together will form the basis for constraints.

To answer your question - We simply cannot build a chip without any prior spec. It would be the dumbest thing to try in the real world.

If you have only clock period in hand and if you are working in a company, Then ask your boss or the system engineer to give the spec. You can start with the system engineer and then discuss with the rest.
If you are a student then you can simply assume any value for clock uncertainty, jitter etc to get timing closure and finish your project. You can assume a drive strength of BUF4 for Input ports and a output load of 200fF as a starting point. There is not a lot of theory behind these values.
Click to expand...

I have a question. What would be the specification/constraints if we are doing an academic project and wanted to tape out the design? How do we derive the spec/constraints?

Thank you.
 

hairo said:
I have a question. What would be the specification/constraints if we are doing an academic project and wanted to tape out the design? How do we derive the spec/constraints?

Thank you.
Click to expand...

For academic projects, it is the prof or course instructor's responsibility to clearly define scope and spec of the project. If your prof/instructor doesn't give you enough details then most likely he has copied over the project req from some US univ and probably did a bad job with the copy. For students, the option is to keep using guesstimated values. Like I said earlier you can start with a drive of BUF4 and a load of 200fF. If that doesn't work out, you simply keep relaxing the values until you get signoff. Same kind of guesstimate will work for all other parameters like uncertainty, clock period, area etc. Or you can also refer previous projects from seniors and adjust the values accordingly,
 
it can vary from company to company and design team to designteam.
Few people agree with 40-60, and few agree with 50-50. So its like they are not using any timebudgetting tool .. they have their standard for deciding this %
 

what Birdy has explained below is near to this , but this is not related to 40% or 50% decision on clk (which for time budgeting) and hence is more towards load numbers and cap limit for inputs. you can say something do for un-registered in-outs. you check also set_load and set_max_capacitance for these kind of pins.
 

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