[SOLVED] Verilog & FPGA Interview

Hello everyone!

I'm a final year undergraduate electrical engineering student, applying for jobs. Last semester I developed a keen interest for Verilog during my course Digital System Design. We used Verilog along with Spartan3 FPGAs.

I was hoping the good people here could guide me as to what type of questions would be asked during a "Verilog Engineer" job interview. What things and concepts shall I prepare well for before walking into the interview room?

Thanks to everybody who responds!

The particular job for which I am asking this question has the following information attached:

Job Description:
We require experienced embedded system engineers with hands on experience of Verilog HDL. Experience on Xilinx and Altera high end FPGAs is required.

Skills Required:
- Verilog
- High end FPGA based system design
- Verification and floor planning
- Various CPU cores experience

it depends of the on the exact job, but the following are common:
* describe blocking vs non-blocking. near 100% chance this will come up.
* code examples that infer latches. near 100% chance on this one as well.
If you miss either of the above two, i don't think you would be considered.

* description of setup/hold on FF's. high chance.
* description of longest path, pipelining.
* async vs sync signals, metastability.
* explanation of timing constraints, multi-clock domain designs.
* parameterized modules.
* routing issues, fan-in/fan-out.
* PLL/DCM/MMCM clocking modules.
* c-slow, retiming -- rare.

In general, you will also be expected to have some familiarity with SPI/I2C/RS232/etc... I also suggest reading Xilinx's GTP/GTX user guides (Virtex-5/6), as these cover some of the basics of "modern" high-speed protocols -- SGMII/XAUI/SRIO/PCIe/10GBASE-X/interlaken.
Depending on the field, you may need to know a little about basic DSP. FIR/IIR filter implementations. IIR filters form a good trick-question for pipelining, and form a good starting point for questions on c-slow.

Ideally, you will have read and made a few demo designs from the XST/Quartus user guides, which have style guidelines. College projects tend to work with poor design practices, and often fail to teach good design practices at all (as it isn't required for the toy designs).

its very hard to determine what will be asked. Each place will have a mix of people with different coding styles. Verilog in particular has some odd syntax features that are rarely used. Oddities like udp/repeat may come up, but really aren't relevant. Likewise, some designers will still be using older tools due to Xilinx's lack of support, or because there was no reason to learn a new style.

obviously you'd be expected to know a bit about floor-planning. This is more common with the Virtex parts. Sparse components -- mainly BRAMs and DSPs -- are in fixed locations and uniformly distributed. However, modules tend to be overweigthed in terms of logic, BRAMs, or DSP. This leads to routing issues where the BRAMs can't be located near the logic they drive. In complex designs, placement becomes a key factor in meeting timing. Floorplanning is one method to hint at where logic/BRAM/DSPs should be placed (mainly BRAMs/DSPs).

If I were a interviewer and interviewing for an entry level position, I would ask questions on fundamentals such as how transistor works, how we can design FSM, etc.
For junior, but not entry level engineers, I would ask about metastability, timing related questions such as what would you do if a design does not meet its timing goal, resource optimization, verification methods, tool related questions.
Hope it helps...

Thank you!!