[Moved] WLM vs increasing frequency

Hi All,

During synthesis, is it useful to increase a clock frequency instead of using WLM? If this is the case, what merging should be added to the clock frequency? What's about the clock uncertainty?

Thank you!

Re: WLM vs increasing frequency

Could you elaborate further? What are you synthesizing?

I'm about a logic synthesis... This question I was asked during the last interview - "How is it possible make a synthesis of RTL without WLM?"
My answer was "If there is no a suitable WLM then increase in clock frequency may help". The next question was "How would you increase the frequency?" I've answered "by 20%", but I'm not sure whether this was the right answer.
So, please comment

"If there is no a suitable WLM then increase in clock frequency may help"

Click to expand...

Yes, it can help. Try to increase the frequency as mush as possible, but to keep WNS near zero (keep slack slightly negative). If you have big WNS - it means, that synthesis tools unsuccesfully tried to optimise your design - it lead to big number of additional buffers, cells will be with excessive driving strength etc (you will get big netlist with still big WNS). What it means "slightly negative" - it's up to you (let's say about 10ps).

Thank you!
I have another question... Let's say I've applied boundary (input/output) constraints on the module and got a big WNS. Would it help to apply additional constraints on the internal critical path logic (let's say max_delay constraints) in order to decrease the slack?

---------- Post added at 11:19 ---------- Previous post was at 10:46 ----------

What techniques to decrease slacks during the logic synthesis?

---------- Post added at 11:47 ---------- Previous post was at 11:19 ----------

What it means "slightly negative" - it's up to you (let's say about 10ps)

Click to expand...

Should this number be depended on the clock frequency? Let's say a slack of 1% of the clock frequency should be considered as a "big slack"? What's about 0.5%?
Should the "slight negative" values be considered as the same for the Hold and SetUp slacks? I mean, should the 10pS slacks be "acceptable" for the Setup Violations as well as Hold Violations?
Thank you!

Would it help to apply additional constraints on the internal critical path logic (let's say max_delay constraints) in order to decrease the slack?

Click to expand...

In such case (you have big WNS, but still want to decrease the salck on the other paths) try to play with set_critical_range (set it to the bigger value). By default, if tool can not reduces the WNS, it will not spent much time on decreasing slack on other paths. set_critical_range change such behaviour.

Should this number be depended on the clock frequency?

Click to expand...

Yes, but I do not know the magic number

Should the "slight negative" values be considered as the same for the Hold and SetUp slacks?

Click to expand...

First of all, the hold does not depend on frequency (only setup depends). The hold may depened on frequency if you have several clocks with different freqs, and the hold are on cross-clocking path. Another point, is that it will be better, to fix hold on post-CTS (or post-route) stage. It is too early to fix hold during synthesis, it will lead to excessive numbers of buffers (delay cells). Many hold vios will be fixed by taking into account the real RC values of routed wires.

If you still want to fix hold during synthesis, it is better to have not any hold WNS. Only zero or positive slack. It is safely.

"set_critical_range" - what exactly does this command? What are default and recommended values?

Critical range specifies a margin of delay for path groups in optimiza-
tion. This must be a positive float number or 0.0. A critical range
of 0.0 means that only the most critical paths (the ones with the worst
violation) are optimized. If you specify a nonzero critical range,
near-critical paths within that amount of the worst path will also be
optimized, if possible.

Use "man" command inside the tools (man set_critical_range).

Thank you oratie! I currently do not have an access to Synopsys tools and cannot run 'man' on the commands. Thank you again for your great comments and answers

Hi Fnds,

can you explain how WLM depends on Frequency.The usage of WLM is only for estimation of timing. By increasing the frequency who to get RC values with out using WLM.(If you may consider ZERO WIRE LOAD models also how it will depends on frequency). By increasing the frequency how to achieve rc vales.

Re: WLM vs increasing frequency

How to guide the tool to use ZERO WLM? As far as I know the WLM is chosen by the tool automatically... So, how to guide the tool for using a certain WLM? Thank you!