pls help me solve the error of bad synchronous description of signal "ones"

sandeshrai · Mar 30, 2012

Code VHDL - [expand]
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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    00:13:44 03/31/2012 
-- Design Name: 
-- Module Name:    visitor_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity visitor_counter is
    Port ( --sys_clk : in  STD_LOGIC;
           sensor_1 : in  STD_LOGIC :='0';
           sensor_2 : in  STD_LOGIC :='0';
           rst : in  STD_LOGIC;
--            H : out  STD_LOGIC_vector(3 downto 0);
              T : out  STD_LOGIC_vector(3 downto 0);
              O : out  STD_LOGIC_vector(3 downto 0));
end visitor_counter;
 
architecture Behavioral of visitor_counter is
 
--  signal clk1 : std_logic;
--  signal visitor_count : integer :=0;
    signal ones, tens : integer :=0;
--  signal hundreds : integer :=0;
--  COMPONENT clk_div
--  PORT(
--      sys_clk : IN std_logic;          
--      q : OUT std_logic
--      );
--  END COMPONENT;
 
begin
 
--  Inst_clk_div: clk_div PORT MAP(
--      sys_clk => sys_clk,
--      q => clk1 
--  );
 
process (rst, sensor_1, sensor_2)
begin
 
if rst='1' then
    ones<= 0;
    tens<= 0;
--  hundreds<= 0;
elsif rising_edge(sensor_1) and rising_edge(sensor_2) then
    ones<=ones;
    tens<=tens;
elsif rising_edge(sensor_1) then 
    ones <= ones + 1 ;
--  if ones>9 then
--      tens<=tens+1;
--      ones<=0;
--      if tens>9 then
--          hundreds<=hundreds+1;
--          tens<=0;
--      end if;
--  end if;
elsif rising_edge(sensor_2) then 
    ones <= ones - 1 ;
--  if ones<0 then
--      tens<=tens-1;
--      ones<=9;
--      if tens<0 then
--          hundreds<=hundreds-1;
--          tens<=9;
--      end if;
--  end if;
    
else 
 
ones <= ones;
tens <= tens;
--hundreds <= hundreds;
 
end if;
 
--case hundreds is
--when 0 => 
--  H<="0000";
--when 1 =>
--  H<="0001";
--when 2 =>
--  H<="0010";
--when 3 =>
--  H<="0011";
--when 4 =>
--  H<="0100";
--when 5 =>
--  H<="0101";
--when 6 =>
--  H<="0110";
--when 7 =>
--  H<="0111";
--when 8 =>
--  H<="1000";
--when others =>
--  H<="1001";
--  hundreds <=0;
--end case;
 
case tens is
    when 0 => 
    T<="0000";
    when 1 =>
    T<="0001";
    when 2 =>
    T<="0010";
    when 3 =>
    T<="0011";
    when 4 =>
    T<="0100";
    when 5 =>
    T<="0101";
    when 6 =>
    T<="0110";
    when 7 =>
    T<="0111";
    when 8 =>
    T<="1000";
    when 9 =>
    O<="1001";
    when 10 =>
--  hundreds<=hundreds+1;
    tens <=0;
    when others =>
--  hundreds<=hundreds-1;
    tens <=9;
end case;
 
case ones is
when 0 => 
    O<="0000";
when 1 =>
    O<="0001";
when 2 =>
    O<="0010";
when 3 =>
    O<="0011";
when 4 =>
    O<="0100";
when 5 =>
    O<="0101";
when 6 =>
    O<="0110";
when 7 =>
    O<="0111";
when 8 =>
    O<="1000";
when 9 =>
    O<="1001";
when 10 =>
    tens<=tens+1;
    ones <=0;
when others =>
    tens<=tens-1;
    ones <=9;
end case;
end process;
 
end Behavioral;

shaiko · Mar 30, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

Please explain what you want your code to do...

You should strongly consider using a clock and making your logic synchronous.
I.E evaluate all data signal under

if rising_edge ( clock ) then

as opposed to:

if rising_edge ( not_a_clock_signal ) then

K-J · Mar 30, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

Problem is here...

Code:

elsif rising_edge(sensor_1) and rising_edge(sensor_2) then
    ones<=ones;
    tens<=tens;
elsif rising_edge(sensor_1) then

You must
- Pick one (and only one) signal to have for the 'rising_edge'
- You must use one (and only one) 'rising_edge' function in an 'elsif' branch (and no, you cannot use 'rising' and 'falling' edge either...only one of them)
- You must have one (and only one) 'elsif' branch

Then you'll have a synchronous description

Kevin Jennings

sandeshrai · Mar 30, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

shaiko said:
Please explain what you want your code to do...

You should strongly consider using a clock and making your logic synchronous.
I.E evaluate all data signal under

if rising_edge ( clock ) then

as opposed to:

if rising_edge ( not_a_clock_signal ) then

shaiko.... i just want to make an input controlled BCD counter... not a clock controlled.... it should increment when i give sensor_1 and decrement when i give sensor_2.......
pls help me out in solving this problem......

---------- Post added at 02:19 ---------- Previous post was at 02:09 ----------

K-J said:
Problem is here...

Code:

elsif rising_edge(sensor_1) and rising_edge(sensor_2) then ones<=ones; tens<=tens; elsif rising_edge(sensor_1) then

You must
- Pick one (and only one) signal to have for the 'rising_edge'
- You must use one (and only one) 'rising_edge' function in an 'elsif' branch (and no, you cannot use 'rising' and 'falling' edge either...only one of them)
- You must have one (and only one) 'elsif' branch

Then you'll have a synchronous description

Kevin Jennings

thanks for the help, I tried using only one rising_edge function with one elsif as You asked me to but the problem still persists....
I would we grateful to you, if you suggest me some different logic for my requirement....
I need to make an input controlled BCD counter.... on rising edge of sensor_1 it should increment and on rising edge of sensor_2 it should decrement......
thanks a lot......

K-J · Mar 31, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

sandeshrai said:
thanks for the help, I tried using only one rising_edge function with one elsif as You asked me to but the problem still persists....

That's because you didn't do as I said

I would we grateful to you, if you suggest me some different logic for my requirement....

Different than what? You say you changed your code, but you didn't post it.

I need to make an input controlled BCD counter.... on rising edge of sensor_1 it should increment and on rising edge of sensor_2 it should decrement

If you use the 'rising_edge' function of 'sensor_1' and 'sensor_2' then you will never succeed...because that violates the rules that I gave you before. Here is something for you to ponder that will help:
- Imagine that you have a signal called 'sensor1_delayed_by_10_ns' which, as the name implies exactly mimics your 'sensor_1' signal, but is magically delayed in time by exactly 10 ns.
- Compute the function sensor_1 and not(sensor1_delayed_by_10_ns). This signal will be a 10 ns wide pulse that goes high precisely at the rising edge of 'sensor_1'. The output of this function is essentially the same thing as detecting the rising_edge of 'sensor_1'.

So let's see what we can do to create 'sensor1_delayed_by_10_ns' without any magic.
- Imagine that you have a free running clock signal that repeats every 10 ns. Call this signal 'clock'.
- Bring the signal 'sensor_1' into the input of a flip flop. Take the output of that flip flop (call it 'Q1') and feed it into the input of a second flip flop. Call the output of that flip flop 'Q2'
- Compute the function 'Q1' and not(Q2). The output of this function is essentially the same as the output of the function that used 'sensor_1' and the magically created 'sensor1_delayed_by_10_ns'...but it does so without any magic. This implies that the output of this function is also essentially the same thing as detecting the rising edge of 'sensor_1'.
- Now imagine using this in the following form:

Code VHDL - [expand]
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process(clock)
begin
   if rising_edge(clock) then
      if ((Q1 = '1') and (Q2 = '0')) then
          -- Anything here will only be executed on precisely one clock cycle which corresponds to
          -- the time of the rising edge of 'sensor_1'
      elsif (....) -- Think you can figure out how to do the same type of thing with sensor_2
         --- Anything here will only be executed on precisely one clock cycle which corresponds to
          -- the time of the rising edge of 'sensor_2'
      end if;
   end if;
end process;

Got it? If not,
- Post your latest effort
- Describe exactly what you see as the problem in terms of the signals that are wrong and under what conditions

Kevin Jennings

sandeshrai · Mar 31, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

Thanks a lot Kevin for the help. This is what I have done after reading your suggestions. It has removed the error but will it serve my purpose? Is there any need for making any change in it? Please do let me know. Just asking for a last favor.

Code VHDL - [expand]
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entity visitor_counter is
    Port ( --sys_clk : in  STD_LOGIC;
           sensor_1 : in  STD_LOGIC ;
           sensor_2 : in  STD_LOGIC ;
           rst : in  STD_LOGIC;
--            H : out  STD_LOGIC_vector(3 downto 0);
              T : out  STD_LOGIC_vector(3 downto 0);
              O : out  STD_LOGIC_vector(3 downto 0));
end visitor_counter;
 
architecture Behavioral of visitor_counter is
 
--  signal clk1 : std_logic;
--  signal visitor_count : integer :=0;
    signal ones, tens : integer :=0;
--  signal hundreds : integer :=0;
    signal sensor_1_prev, sensor_2_prev : std_logic :='0';
--  COMPONENT clk_div
--  PORT(
--      sys_clk : IN std_logic;          
--      q : OUT std_logic
--      );
--  END COMPONENT;
 
begin
 
--  Inst_clk_div: clk_div PORT MAP(
--      sys_clk => sys_clk,
--      q => clk1 
--  );
 
process (rst, sensor_1, sensor_2)
begin
 
if rst='1' then
    ones<= 0;
    tens<= 0;
--  hundreds<= 0;
end if;
if sensor_1='1' and sensor_1_prev='0' then 
    ones <= ones + 1 ;
--  if ones>9 then
--      tens<=tens+1;
--      ones<=0;
--      if tens>9 then
--          hundreds<=hundreds+1;
--          tens<=0;
--      end if;
--  end if;
    sensor_1_prev<='1';
elsif sensor_1='0' then
    sensor_1_prev<='0';
end if;
if sensor_2='1' and sensor_2_prev='0' then 
    ones <= ones - 1 ;
--  if ones<0 then
--      tens<=tens-1;
--      ones<=9;
--      if tens<0 then
--          hundreds<=hundreds-1;
--          tens<=9;
--      end if;
--  end if;
    sensor_2_prev<='1';
elsif sensor_2='0' then
    sensor_2_prev<='0';
end if; 
--else 
--
--ones <= ones;
--tens <= tens;
--hundreds <= hundreds;
 
--end if;
 
--case hundreds is
--when 0 => 
--  H<="0000";
--when 1 =>
--  H<="0001";
--when 2 =>
--  H<="0010";
--when 3 =>
--  H<="0011";
--when 4 =>
--  H<="0100";
--when 5 =>
--  H<="0101";
--when 6 =>
--  H<="0110";
--when 7 =>
--  H<="0111";
--when 8 =>
--  H<="1000";
--when others =>
--  H<="1001";
--  hundreds <=0;
--end case;
 
case tens is
    when 0 => 
    T<="0000";
    when 1 =>
    T<="0001";
    when 2 =>
    T<="0010";
    when 3 =>
    T<="0011";
    when 4 =>
    T<="0100";
    when 5 =>
    T<="0101";
    when 6 =>
    T<="0110";
    when 7 =>
    T<="0111";
    when 8 =>
    T<="1000";
    when 9 =>
    T<="1001";
    when 10 =>
--  hundreds<=hundreds+1;
    tens <=0;
    when others =>
--  hundreds<=hundreds-1;
    tens <=9;
end case;
 
case ones is
when 0 => 
    O<="0000";
when 1 =>
    O<="0001";
when 2 =>
    O<="0010";
when 3 =>
    O<="0011";
when 4 =>
    O<="0100";
when 5 =>
    O<="0101";
when 6 =>
    O<="0110";
when 7 =>
    O<="0111";
when 8 =>
    O<="1000";
when 9 =>
    O<="1001";
when 10 =>
    tens<=tens+1;
    ones <=0;
when others =>
    tens<=tens-1;
    ones <=9;
end case;
end process;
 
end Behavioral;

Thanks and regards,
Sandesh Rai

---------- Post added at 12:26 ---------- Previous post was at 12:22 ----------

Actually I can't access the FPGA kit for the next two days, so that I could check out myself. That's why asked from you.

K-J · Mar 31, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

sandeshrai said:
This is what I have done after reading your suggestions.

You didn't follow most of my suggestions, including he most important.

I suggested...

Code VHDL - [expand]
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process(clock)

You have...

Code VHDL - [expand]
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process (rst, sensor_1, sensor_2)

I suggested...

Code VHDL - [expand]
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process(clock)
begin
   if rising_edge(clock) then
      if ((Q1 = '1') and (Q2 = '0')) then
          -- Anything here will only be executed on precisely one clock cycle which corresponds to
          -- the time of the rising edge of 'sensor_1'
      elsif (....) -- Think you can figure out how to do the same type of thing with sensor_2
         --- Anything here will only be executed on precisely one clock cycle which corresponds to
          -- the time of the rising edge of 'sensor_2'
      end if;
   end if;
end process;

You have...

Code VHDL - [expand]
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process (rst, sensor_1, sensor_2)
begin
    if rst='1' then
        -- Stuff
    end if;
    if sensor_1='1' and sensor_1_prev='0' then 
        -- Stuff
        sensor_1_prev<='1';
    elsif sensor_1='0' then
        sensor_1_prev<='0';
    end if;
    if sensor_2='1' and sensor_2_prev='0' then 
        -- Stuff
        sensor_2_prev<='1';
    elsif sensor_2='0' then
        sensor_2_prev<='0';
    end if; 
end process;

I suggested...
- Bring the signal 'sensor_1' into the input of a flip flop. Take the output of that flip flop (call it 'Q1') and feed it into the input of a second flip flop. Call the output of that flip flop 'Q2'

What you have for creating the delayed version of the sensor signals in your code above does not implement this at all. Re-read the bullet above. The delayed version of the sensor signals should always represent the sensor signals delayed by one clock (Q1 above) or two clocks (Q2 above). That would mean that there is no dependency on any other signals. Look at your code where you do the assignments...you will only get there under certain conditions, not others.

The other problem with what you have is that you have compared to my suggestion is that you have

Code VHDL - [expand]
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if sensor_1='1' and sensor_1_prev='0' then

But I said to take the sensor inputs and put them through two flip flops. What you have is looking at the sensor input and comparing it to the sensor input sort of delayed by one clock cycle...not two. I'm pretty sure that your sensor inputs are not synchronized with clock which means that you absolutely must synchronize it first before ever using it. Your code will use the raw sensor input in at least two places: the 'if statement' and for creating the '*_prev' signal. That is not right. You need to delay it twice and then use it like this...

Code VHDL - [expand]
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if sensor_1_prev='1' and sensor_1_prev_2='0' then

The only place where you should ever use 'sensor_1_prev' is to create the signal 'sensor_1_prev_2' (or whatever you want to call the 'delayed by 2' clock cycles version of the signal.

It has removed the error but will it serve my purpose? Is there any need for making any change in it?

The way to answer the question about whether it serves your purpose and whether changes need to be made is through simulation and perusal of the synthesis warnings that came out that you ignored. To be blunt though, 'no', what you have will not work.

The only change I would add to the structure that I originally posted is to add the reset branch. I didn't have that in the last posting because it isn't relevant to the discussion about how to get rid of the incorrect usage you had with the rising_edge function that was causing the error.

Code VHDL - [expand]
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if rising_edge(clock) then
      if (Rst = '1') then
         -- Stuff
      elsif ((Q1 = '1') and (Q2 = '0')) then
      ... (as shown in previous post)

Kevin Jennings

sandeshrai · Mar 31, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

Sir, Please have a look at the code attached. Now I think, I have followed everything what you asked me to do (as far as I can make out, please correct me if I am wrong, the way you have been doing throughout the thread).

Code:

entity visitor_counter is
    Port ( sys_clk : in  STD_LOGIC;
           sensor_1 : in  STD_LOGIC ;
           sensor_2 : in  STD_LOGIC ;
           rst : in  STD_LOGIC;
--			  H : out  STD_LOGIC_vector(3 downto 0);
			  T : out  STD_LOGIC_vector(3 downto 0);
			  O : out  STD_LOGIC_vector(3 downto 0));
end visitor_counter;

architecture Behavioral of visitor_counter is

	signal clk1 : std_logic;
--	signal visitor_count : integer :=0;
	signal ones, tens : integer :=0;
--	signal hundreds : integer :=0;
	signal sensor_1_prev_1, sensor_1_prev_2, sensor_2_prev_1, sensor_2_prev_2 : std_logic :='0';
	COMPONENT clk_div
	PORT(
		sys_clk : IN std_logic;          
		q : OUT std_logic
		);
	END COMPONENT;

begin

	Inst_clk_div: clk_div PORT MAP(
		sys_clk => sys_clk,
		q => clk1 
	);

process (clk1)
begin
if rising_edge(clk1) then
sensor_1_prev_1<=sensor_1;
sensor_1_prev_2<=sensor_1_prev_1;
sensor_2_prev_1<=sensor_2;
sensor_2_prev_2<=sensor_2_prev_1;
	if rst='1' then
		ones<= 0;
		tens<= 0;
--		hundreds<= 0;
	elsif (sensor_1_prev_1='1') and (sensor_1_prev_2='0') then 
	ones <= ones + 1 ;
		if ones>9 then
			tens<=tens+1;
			ones<=0;
--			if tens>9 then
--				hundreds<=hundreds+1;
--				tens<=0;
--			end if;
		end if;
	elsif (sensor_2_prev_1='1') and (sensor_2_prev_2='0') then 
	ones <= ones - 1 ;
		if ones<0 then
			tens<=tens-1;
			ones<=9;
--			if tens<0 then
--				hundreds<=hundreds-1;
--				tens<=9;
--			end if;
		end if;
	end if;	
--else 
--
--ones <= ones;
--tens <= tens;
--hundreds <= hundreds;

end if;
end process;

process (ones, tens)
begin

case ones is
	when 0 => 
	O<="0000";
	when 1 =>
	O<="0001";
	when 2 =>
	O<="0010";
	when 3 =>
	O<="0011";
	when 4 =>
	O<="0100";
	when 5 =>
	O<="0101";
	when 6 =>
	O<="0110";
	when 7 =>
	O<="0111";
	when 8 =>
	O<="1000";
	when others =>
	O<="1001";
end case;

case tens is
	when 0 => 
	T<="0000";
	when 1 =>
	T<="0001";
	when 2 =>
	T<="0010";
	when 3 =>
	T<="0011";
	when 4 =>
	T<="0100";
	when 5 =>
	T<="0101";
	when 6 =>
	T<="0110";
	when 7 =>
	T<="0111";
	when 8 =>
	T<="1000";
	when others =>
	T<="1001";
end case;

--case hundreds is
--when 0 => 
--	H<="0000";
--when 1 =>
--	H<="0001";
--when 2 =>
--	H<="0010";
--when 3 =>
--	H<="0011";
--when 4 =>
--	H<="0100";
--when 5 =>
--	H<="0101";
--when 6 =>
--	H<="0110";
--when 7 =>
--	H<="0111";
--when 8 =>
--	H<="1000";
--when others =>
--	H<="1001";
--	hundreds <=0;
--end case;



end process;

end Behavioral;

Sorry to take time to make the adjustments, forgive me if I ever made you lose your temper. I am just a newbie in VHDL coding. I joined Edaboard to get a help for my project "FPGA based Visitor Counter". Unexpectedly, got such a precious and valuable help from it via the great KEVIN JENNINGS. Thank you so much sir for your time, support and guidance. You deserve a *SALUTE*. You have earned a place in the Acknowledgments part of my PROJECT and most importantly in my heart. *** bless you.
Thanks and Regards
Sandesh Rai

std_match · Apr 1, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

I guess that both sensors could be activated at the same time. Your current code can not handle that.

One solution is that you place the check for sensor 2 in it's own "if" clause, instead as an "elsif" to sensor 1".

Then you will have the problem that you can't both increment and decrement a signal in a process, since only the last operation will have effect.
There are different ways to solve this. One is that you use variables instead of signals for the counters.

I try to avoid variables that have "memory" from one clock cycle from the previous, since it is difficult to visualize what the synthesis tool will do.
In this case you could assign the current counters (signals) to variables at the beginning of the process, and do the increment/decrement on the variables.
At the end of the process, you can assign the results back to the signals.

It will work if you skip the signals and use only variables for the counters.

Another solution is that you add a new "if" at the beginning of the "elsif"-chain that check for an edge on both sensors. When that "if" is true, you do nothing! (a null statement).
I think this will be my final recommendation, since the code should be easy to understand.

EDIT:
Asynchronous inputs should be clocked through 2 flip-flops before you use them. To detect an edge in a safe way you should add one extra flip-flop. Then you have 3 flip-flops in a chain for each input. You detect the edge by comparing the values in the last two stages (as your code already does).

K-J · Apr 1, 2012

Re: pls help me solve the error of bad synchronous description of signal "ones"

Below is a testbench (entity tb_visitor_counter) that you can use to verify if things are working properly. Simply compile it, load it into the simulator and run -all. The testbench will
- Generate all of the stimulus to your entity
- Print out messages as it gets to various parts of the test

If you put all of the signals from tb_visitor_counter into a wave window you will see the following:
- Signal 'Test_Phase' which simply gives a visual indicator as to what part of the test is running at any time
- A 'truth' value for the expected value of the count (signal My_Count)
- When you're counting (up or down), you're not handling the counting correctly 'O' is equal to 9.
- As std_match pointed out, you're not handling the case where you have simultaneous edges on sensor_1 and sensor_2. Take a look at how this is handled when I compute 'My_Count'. You will need to embed a similar check to make sure that you're not at a rising edge on sensor_2 before doing an increment due to a rising edge on sensor_1.

Note also how a testbench can freely violate all of the rules that apply to your counter that I imposed on you. That's because a testbench is never synthesized into real hardware, it is purely for simulation purposes.

Kevin Jennings

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity tb_visitor_counter is
end tb_visitor_counter;
architecture RTL of tb_visitor_counter is
    signal sys_clk:     STD_LOGIC   := '0';
    signal sensor_1:    STD_LOGIC ;
    signal sensor_2:    STD_LOGIC ;
    signal rst:         STD_LOGIC;
    signal T:           STD_LOGIC_vector(3 downto 0);
    signal O:           STD_LOGIC_vector(3 downto 0);
 
    signal Sim_Complete:    std_ulogic := '0';
    signal My_Count:        integer := 0;
    type t_Test_Phase is (Reseting, Test_Sensor_1, Test_Sensor_2, Test_Simultaneous, No_Counting, Count_Once);
    signal Test_Phase:  t_Test_Phase;
begin
    sys_clk <= not(Sim_Complete) and not(sys_clk) after 10 ns;
    rst     <= '1', '0' after 30 ns;
 
    MAIN : process
    begin
        Test_Phase  <= Reseting;
        sensor_1 <= '0';
        sensor_2 <= '0';
        wait until (rst = '0') and rising_edge(sys_clk);
 
        report "Generate some rising edges on sensor_1";
        Test_Phase  <= Test_Sensor_1;
        for i in 1 to 100 loop
            sensor_1 <= '1'; wait until rising_edge(sys_clk);sensor_1 <= '0'; wait until rising_edge(sys_clk);
        end loop;
        wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); wait until rising_edge(sys_clk); wait until rising_edge(sys_clk);
        report "Should have counted up 100 times at this point...does it cause the counter to wrap around?";
 
        Test_Phase  <= Test_Sensor_2;
        for j in 1 to 100 loop
            sensor_2 <= '1'; wait until rising_edge(sys_clk);sensor_2 <= '0'; wait until rising_edge(sys_clk);
        end loop;
        report "Should have counted back down to 0 at this point...did it?";
 
        Test_Phase  <= Test_Simultaneous;
        report "Now let's test to see that the counter does not count when it shouldn't with simultaneous edges on sensor_1 and sensor_2";
        for i in 1 to 10 loop
            sensor_1 <= '1'; sensor_2 <= '1'; wait until rising_edge(sys_clk); sensor_1 <= '0'; sensor_2 <= '0'; wait until rising_edge(sys_clk);
        end loop;
 
        Test_Phase  <= No_Counting;
        report "Now let's test to see that the counter does not count when it shouldn't with sensor_1 and sensor_2 always 0";
        sensor_1 <= '0'; sensor_2 <= '0'; 
        for i in 1 to 10 loop
            wait until rising_edge(sys_clk); wait until rising_edge(sys_clk);
        end loop;
 
        Test_Phase  <= Count_Once;
        report "Now let's test to see that the counter does not count more than once when it shouldn't with sensor_1 and sensor_2 always 1";
        sensor_1 <= '1'; sensor_2 <= '1'; 
        for i in 1 to 10 loop
            wait until rising_edge(sys_clk); wait until rising_edge(sys_clk);
        end loop;
 
        Sim_Complete <= '1';
        report "Simulation complete";
        wait;
    end process;
 
    process
    begin
        wait until rising_edge(sensor_1) or rising_edge(sensor_2) or rising_edge(Sim_Complete);
        if (Sim_Complete = '0') then
            if rising_edge(sensor_1) then
                if not(rising_edge(sensor_2)) then
                    My_Count <= My_count + 1;
                end if;
            elsif rising_edge(sensor_2) then
                My_Count <= My_count - 1;
            end if;
        end if;
    end process;
 
    DUT : entity work.visitor_counter Port map(
        sys_clk => sys_clk,
        sensor_1 => sensor_1,
        sensor_2 => sensor_2,
        rst  => rst,
        T => T,
        O => O);
end RTL;

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pls help me solve the error of bad synchronous description of signal "ones"

sandeshrai

Newbie level 3

shaiko

Advanced Member level 5

K-J

Advanced Member level 2

sandeshrai

Newbie level 3

K-J

Advanced Member level 2

sandeshrai

sandeshrai

Newbie level 3

K-J

Advanced Member level 2

sandeshrai

graphene

sandeshrai

Newbie level 3

std_match

Advanced Member level 4

K-J

Advanced Member level 2

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