Inferring a delays with flip flops

In an asynchronous (clockless) FPGA design - Is it possible to inffer delays using this code :


Will the above work ?

shaiko said:

In an asynchronous (clockless) FPGA design - Is it possible to inffer delays using this code :

Code:

-- I want to delay the trigger signal...

process ( reset , trigger ) 
if reset = '1' then
  Q1 <= '0' ;
elsif rising edge ( trigger  ) then
  Q1 <= '1' ;
end if ;
end process ;

process ( reset , Q1 ) 
if reset = '1' then
  Q2 <= '0' ;
elsif rising edge ( Q1 ) then
  Q2 <= '1' ;
end if ;
end process ;


process ( reset , Q2 ) 
if reset = '1' then
  Q3 <= '0' ;
elsif rising edge ( Q2 ) then
  Q3 <= '1' ;
end if ;
end process ;

Will the above work ?

Click to expand...

If by 'will this work?', you mean will there be a delay between 'trigger' and 'Q3', the answer is 'yes'.
If by 'will this work?', you mean will there be a known or controllable delay between 'trigger' and 'Q3', the answer is 'no'.

The clock to Q delay "is what it is". If your only timing requirement is that the delay from 'trigger' to 'Q3' be greater than 0, you're OK. Those situations those don't show up very often. If your application is such that you need to meet some specific timing requirement for that delay (for example > 1 ns; < 5 ns), you're stuck and your design will be at the mercy of the silicon process, the supply voltage to the device, the local temperature of the die (i.e. PVT).

Whatever happened with trying to generate a clock somehow from your other postings? Does the part you're using not lend itself to creating a clock?

Kevin Jennings

Whatever happened with trying to generate a clock somehow from your other postings? Does the part you're using not lend itself to creating a clock?

Click to expand...

That would've been great.
But I simply don't know how to create a ring oscillator on the Actel device!
Please help me write a proper code for it - that will be of great help to me!