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pwm code in vhdl help

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Zampradeep

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..hi guys..others project is time code generator on fpga and generated time code ....now have to do pwm....here is the code i wrote but not getting output...in code i used /100 counter as actual serial data and /10 to compare it and change duty cycle.....i.e each serial data pluse time=10 times /10 counter output pulse width..given code has some unused signals ignore it....i want siganl of 20% duty cycle...

sorry if any silly mistakes....i am complete newbie to vhdl....should i use /5 conter instead of 10 

Code VHDL - [expand]
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pwmm is 
port(cp,reset : in std_logic;
     dout :out std_logic 
);
end pwmm;
architecture  pwmm_arch of pwmm is
signal divby100: std_logic_vector(3 downto 0):="0000";
signal divby10: std_logic_vector(3 downto 0):="0000";
signal count: std_logic_vector(3 downto 0):="0000";
signal count2:std_logic_vector(3 downto 0):="0010";
signal count5:std_logic_vector(3 downto 0):="0101";
signal count8:std_logic_vector(3 downto 0):="0100";
signal div100: std_logic_vector(3 downto 0):="0000";
 
begin
process(cp)
BEGIN    
if(cp'event and cp= '1') then
if (divby10="1001") then
divby10<="0000";
if(divby100="1001") then
divby100<="0000";
div100<=div100+'1';
else
divby100<=divby100 + '1';
end if;
else
divby10<=divby10+'1';
end if;
END IF;
end process;
process(div100(0))
begin
if(div100(0)'event and div100(0)='1') then
while (COUNT2 > COUNT)
loop
IF   divby100(0)'event and divby100(0)='1'   THEN 
 
 COUNT<=COUNT + '1';
 dout<='1';
end if;
end loop;
dout<='0';
COUNT<="0000";
END IF;
END PROCESS;
END pwmm_ARCH;
 
Last edited by a moderator:

your downfall is the while loop.
signals are only changed when a process hits a wait. So in your while loop it will actually loop forever because count never increases, and divby100 clk event is always true (otherwise how do you think it got into the loo).

You should never use while loops for synthesisable code.
Also, you should never create clocks with logic. You should create clock enables instead.
 

You should consider using spaces and indents in your code to make it more readable.
Compare the following to your originally posted code

Code VHDL - [expand]
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pwmm is 
port(cp,reset : in std_logic;
     dout :out std_logic 
);
end pwmm;
 
architecture  pwmm_arch of pwmm is
signal divby100: std_logic_vector(3 downto 0):="0000";
signal divby10: std_logic_vector(3 downto 0):="0000";
signal count: std_logic_vector(3 downto 0):="0000";
signal count2:std_logic_vector(3 downto 0):="0010";
signal count5:std_logic_vector(3 downto 0):="0101";
signal count8:std_logic_vector(3 downto 0):="0100";
signal div100: std_logic_vector(3 downto 0):="0000";
 
begin
 
process(cp)
BEGIN    
    if(cp'event and cp= '1') then
        if (divby10="1001") then
            divby10<="0000";
            if(divby100="1001") then
                divby100<="0000";
                div100<=div100+'1';
            else
                divby100<=divby100 + '1';
            end if;
        else
            divby10<=divby10+'1';
        end if;
    END IF;
end process;
 
 
process(div100(0))
begin
    if(div100(0)'event and div100(0)='1') then
        while (COUNT2 > COUNT)
        loop
            IF   divby100(0)'event and divby100(0)='1' THEN 
                COUNT<=COUNT + '1';
                dout<='1';
            end if;
        end loop;
        dout<='0';
        COUNT<="0000";
    END IF;
END PROCESS;
 
END pwmm_ARCH;
 

...1st sorry its my 1st post so didnt know that we have to use tags for code...@tricky bro then what should i use if instead of while...is there any other itiration statement keyword...
 

Iterative loops are not condusive to real world logic.
I suggest you draw the circuit you are trying to acheive, and then think how that might translate to VHDL. Dont write the VHDL before knowing what the circuit it.
 

..Plz bro help..logic is whenever serial data changes state it enters into to the process and at every clock pluse of /10 counter .signal count is incremented and condition is checked..
 

like I said - draw the circuit on paper first. VHDL is a hardware description language, not a programming language. If you dont know what the circuit is, how do you expect to describe it.

This is also a common homework assignment - so dont expect us to do your work for you.
 
..Tricky bro i never asked u to give me code.... just seeking hint where i am going wrong..circuit goes like this
serial data of 100 hz
clock of 1khz
and (0-10)counter
4 bit comparator...

Reference->-----comp
Clock->counter->comp

if counter>reference
dout=0
reference of signal of
0010
and serial data as enable..
Comp compares the reference signal with 4 bit counter output ..when more 2 pluses are passed..out is zero..
 

to make things easier, you could start by eliminating the std_logic_vectors for the counters and replacing them with integer, natural or unsigned.

Write a counter, let it run from 0 to max_countervalue, set the dout signal, when the counter reaches the desired value, reset your dout signal (port).

If you translate this piece of text to vhdl/verilog, you'll have the desired PWM.

When the set value of the PWM is serial data, you'll need a temporaty register used as shift register. Depending on the serial data clock rate on how fast this will be updated. When the set value is clocked in, you'll need an enable signal to copy the temp register to the desired value.
 
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