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Write a signal at a specific clock in VHDL

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uselessmail

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How do I write a signal in VHDL such that
Code:
Sig_A <= Sig_B
is within a clocked process and it is written at every 10th clock period if the clock frequency is say 100 Mhz?
 

this bit of your homework comes for free.

Code:
if counter = 10 then
  siga <= sigb;
end if;

ill let you do the rest yourself. come back when you've at least attempted it yourself and are stuck.
 

this bit of your homework comes for free.

Code:
if counter = 10 then
  siga <= sigb;
end if;

ill let you do the rest yourself. come back when you've at least attempted it yourself and are stuck.

I did figure it out by then actually! Thanks a lot mate! I really appreciate it!
The code I used:

Code:
process(clk)
	variable counter: integer range 0 to 9 :=0;
	begin
		if rising_edge(clk) then
			counter := counter + 1;
			
			if counter = 9 then
				Sig_A <= Sig_B;
			end if;			
			
		end if;
	end process;
 

If you want the assignment to happen every 10th clock cycle, you must also add code so the counter wraps back to zero.

An integer variable/signal does not automatically wrap back to the lowest value when you increment from the highest value.
 
If you want the assignment to happen every 10th clock cycle, you must also add code so the counter wraps back to zero.

An integer variable/signal does not automatically wrap back to the lowest value when you increment from the highest value.

Oh Thank you!!!
 

If you want the assignment to happen every 10th clock cycle, you must also add code so the counter wraps back to zero.

An integer variable/signal does not automatically wrap back to the lowest value when you increment from the highest value.

Yeah correct, but this wrap up is not required when the range includes all values (2powerN)
 

Yeah correct, but this wrap up is not required when the range includes all values (2powerN)

It does when the type is an integer. Otherwise you'll get an out of range error when you try and simulate it. No problems on hardware though.
 

I did figure it out by then actually! Thanks a lot mate! I really appreciate it!
The code I used:

Code:
process(clk)
	variable counter: integer range 0 to 9 :=0;
	begin
		if rising_edge(clk) then
			counter := counter + 1;
			
			if counter = 9 then
				Sig_A <= Sig_B;
			end if;			
			
		end if;
	end process;

But this code will not wait for 10 clocks. only 9 clocks though. Increase the range to 15 (since no one is going to question, as hardware will take even if you dont change) and counter to check for value 10. The problem is this is var, not sig. So '0' is not taken into account
 

it will be, just not on the first run-through.
actually what happens here is the counter is added and compared before a register. If you move the counter to below the comparitor it will work as you expect.
 

yes, exactly. you are right.

I said signal because I've some designers here advising me to use "signals" in place of "variables" and adjust the logic slightly. This is just to gain timing match for your circuit, because variables are little tough at timing predictions.
 

There is nothing wrong with variables, as long as you understand the hardware that will be created by the synthesisor.
The best advice is to stick with signals until you understand what you're doing.
 

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