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ERROR:HDLCompilers:27 - "da.v" line 12 Illegal redeclaration of 'dout1'

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darshankumar

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Code: 
`timescale 1ns / 1ps
module sd(input clk,input en,
                 input [7:0] din1,
                 input [7:0] addr1,
					  input  we,
                 output   [7:0] dout1                                                   
                );  
    parameter RAM_WIDTH =8;
   parameter RAM_ADDR_BITS = 8;
   
 reg [RAM_WIDTH-1:0] bram [(2**RAM_ADDR_BITS)-1:0];
wire[7:0] dout1;
   always @(posedge clk)
      if (en) begin
         if (we)
            bram[addr1] <= din1;
				dout1 <= bram[addr1];
				end
		bram bram1(.clk(clk),
		.we(we),
		.din(din1),
		.addr(addr1),
		.en(en),
		.dout(dout1)
		);
	endmodule

help me out i am getting this error please
 
Last edited by a moderator:

darshankumar said:
output [7:0] dout1

dout1 <= bram[addr1];

.dout(dout1)
Click to expand...

What is that?. You are trying to read the output IO register which is not possible. You should do something like this
Code: 
wire[7:0] dout1_reg;
dout1 <= bram[addr1];
dout1_reg <= bram[addr1];

.dout(dout1_reg);

You create an immediate net for output driver and then read that net. This is meaningful.
 
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