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VHDL- Assigning MSB and LSB of a signal to new signals

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dhanush3005

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How can we extract 4 bit msb and 4 bit lsb of an 8 bit signal 'a1' to two signals 'a2' and 'a3' where a1, a2,a3 are declared as

signal a1 : std_logic_vector(7 downto 0) ;
signal a2 : std_logic_vector(3 downto 0) ;
signal a3 : std_logic_vector(3 downto 0) ; ?
 

How can we extract 4 bit msb and 4 bit lsb of an 8 bit signal 'a1' to two signals 'a2' and 'a3' where a1, a2,a3 are declared as

signal a1 : std_logic_vector(7 downto 0) ;
signal a2 : std_logic_vector(3 downto 0) ;
signal a3 : std_logic_vector(3 downto 0) ; ?

a2 <= a1(7 downto 4);
a3 <= a1(3 downto 0);

Kevin Jennings
 
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