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Hi-Z in std_logic_vector

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TommiRouvali

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Hi,

I am trying to make IO extension board for microcontroller. Any port of XC95108 can be input or output. I had some issues getting design to fit inside XC95108 and so finally ended up design below. Pins work outputs as planned, but they don't seem to go Hi Z mode. Is it valid to scolling 'Z' in std_logic_vector like I do? 


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity main is
    Port ( DIN : in  STD_LOGIC;
              CLK : in  STD_LOGIC;
              WRD : in  STD_LOGIC;
              RDD : in  STD_LOGIC;
              TRIS : in  STD_LOGIC;
              DOUT : out  STD_LOGIC;
              PORTS : inout std_logic_vector(57 downto 0));
end main;
 
architecture Behavioral of main is
 
signal InData : std_logic_vector(51 downto 0);
 
begin
 
process (CLK)
begin
    if (CLK='1' and CLK'EVENT) then
        if (RDD='1') then           
            InData(51 downto 0)<=PORTS(51 downto 0);
        else    
            if(TRIS='1') then
                InData(51 downto 0)<=InData(50 downto 0) & 'Z';
            else
                InData(51 downto 0)<=InData(50 downto 0) & DIN; 
            end if;
            DOUT<=InData(51);           
        end if;
    end if;     
end process;
 
process (WRD)
begin
    if (WRD='1' and WRD'EVENT) then
            PORTS(51 downto 0)<=InData(51 downto 0);
        end if;
end process;
 
end Behavioral;
 
Last edited by a moderator:

You are assigning 'Z' to the internal signal InData. That may work in simulation, but it will probably not work in a real circuit.
Redesign your circuit so you only assign 'Z' directly to the inout port.

I haven't tried to understand exactly what you are doing, but if you want to shift the 'Z' value, you should use another std_logic_vector with only '0' and '1' as output enable signals and do the shifting there.
 
'Z' state must be directly assigned to an INOUT port, it can't be stored in a registered signal.
 
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