Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Sythesible code_Fatal error in a 2d array.

Status
Not open for further replies.

ghostridergr

Member level 1
Joined
Nov 22, 2011
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,590
This was my initial code:
Code:
storing: for k in 0 to 10 loop
          inside: for l in 0 to 10 loop
           sum_of_square_all(k)(l)<=signed(ext(sum_of_square(inp1(k),inp2(l),"000000000000000000000000"),3*N));
          wait for 15 ns;
        end loop inside;
        match(k)<=find_min(sum_of_square_all(k));
     end loop storing;
My question is this: Is this code synthesible? Or only one element can be stored in each clock cycle?
You can what the types at the final code.

If this code is not synthesible, can you suggest me some changes so as to do it.

I am thinking of those:
insert a flag on my code (so as to know when inp1,inp2 arrays are filled) and then put the loop in a individual process (with no wait so as to run all the time). Then having an if clk'event and inside do the assignment. In this case this is my code:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity tb_file_landmark is
  generic
		(N :integer := 8);
		port ( clk:in std_logic
		);
end tb_file_landmark;


architecture TB_ARCHITECTURE of tb_file_landmark is
file IN_1_VECTORS: TEXT open READ_MODE is "input_1.txt";
file IN_2_VECTORS: TEXT open READ_MODE is "input_2.txt";
file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";
--here
type matrix1_t is array(natural range<>) of signed(N-1 downto 0);
type big_matrix is array(natural range<>) of signed(3*N-1 downto 0);
type matrix2d is array (natural range<>) of matrix1_t(0 to 3);
signal sum_of_square_all: matrix2d(0 to 3);
signal inp1,inp2: matrix1_t(0 to 3);
signal a,b: signed(N-1 downto 0):= (others=>'0');
signal match:big_matrix(0 to 3);
signal flag:std_logic:='0';
signal k:integer range 0 to 100:= 0;
signal l:integer range 0 to 100:= 0;



--procedure sum_of_square( signal a,b: in signed(N-1 downto 0);signal  previous_sum:in std_logic_vector(3*N-1 downto 0); signal sum:out std_logic_vector(3*N-1 downto 0)) is
function sum_of_square( a1,b1: in signed(N-1 downto 0); previous_sum:in std_logic_vector(3*N-1 downto 0))return std_logic_vector is     
     variable temp_sum:std_logic_vector(3*N-1 downto 0):=(others=>'0');
     variable diff: signed(N-1 downto 0):=(others=>'0');
	   variable square_diff: std_logic_vector(2*N-1 downto 0):=(others=>'0');
begin
  temp_sum:=previous_sum;
  diff:=a1-b1;
	square_diff:=ext(diff*diff,2*N);
	temp_sum:=ext(temp_sum+square_diff,3*N);
  return temp_sum;
end sum_of_square;

function find_min(row: in matrix1_t(0 to 3)) return signed is
variable temp_min:signed(3*N-1 downto 0);
begin
  temp_min:=row(0);
  checking: for t in 1 to 3 loop
      if  (row(t)<temp_min) then
        temp_min:=row(t);
    end if;
  end loop checking;
  return temp_min;
end find_min;

begin
             
    process
        variable IN_BUF: LINE;
        variable OUT_BUF: LINE;
        variable a_var,b_var : bit_vector(N-1 downto 0):= (others=>'0');
        variable i,j: integer;
        
	--	variable c_var,d_var : bit_vector(N-1 downto 0):= (others=>'0');
  --variable sum_var:std_logic_vector(3*N-1 downto 0):= (others=>'0');
		
    begin
        i:=0;
        j:=0;
        while not ENDFILE(IN_1_VECTORS) loop
            READLINE(IN_1_VECTORS,IN_BUF);
            READ(IN_BUF,a_var);
            a<=signed(to_stdlogicvector(a_var));
            wait for 50 ns;
            inp1(i)<=a;
            i:=i+1;
        end loop;
        while not ENDFILE(IN_2_VECTORS) loop
            READLINE(IN_2_VECTORS,IN_BUF);
            READ(IN_BUF,b_var);
            b<=signed(to_stdlogicvector(b_var));
            wait for 50 ns;
            inp2(j)<=b;
            j:=j+1;
        end loop;
        flag<='1';
        wait;
    end process;
    
    process(clk)
       variable row:integer;
       variable column: integer;
    begin
      if (flag='1') then
        if (clk'event) then
          if ((k<=10) and (l<=10)) then
--############GETTING FATAL ERROR IN HERE##########
            sum_of_square_all(k)(l)<=signed(ext(sum_of_square(inp1(k),inp2(l),"000000000000000000000000"),3*N));
--############GETTING FATAL ERROR IN HERE##########
            k<=k+1;
            l<=l+1;
        end if;
      end if ;
  end if ;
end process;
    
end TB_ARCHITECTURE;

but as you can see I am getting a fatal error in here. Can anyone help me?
 

"wait for" can't be synthesised - an FPGA has no way to delay by an arbitrary amount of time.

Nested loops can be synthesised, but they don't work like loops in procedural programming languages - all iterations will be executed simultaneously. This will cause 11*11 instantiations of your sum_of_square to be generated, which might use up a very large amount of resources. Unless you really need to do the entire operation simultaneously, strongly consider using a clocked process. In general, if you're thinking about using a for loop, you're not thinking about how it maps to hardware.

In pseudo-code,

k=0
l=0
always @(posedge clock) begin
if k <= 10
if l <= 10
l = l + 1;
else
k = k + 1
l = 0
end if
else
finished = 1;
end if

operation_with_k_and_l();
end


You didn't say what the fatal error in the second code example is, but it's a bit closer to what I came up with, except that by incrementing both k and l simultaneously, you would only look at the diagonal.

I suspect that the problem might be that your sum_of_square isn't synthesisable either, but without seeing the error I'm not sure. I'd probably make it a separate module and then control the inputs using register assignments.
 
None of the code you have is synthesisable code:

1. The use of "wait for" statements
2. The use of textio
3. you need "clk'event and clk = '1'" or "rising_edge(clk) to make it synthesise a real register. Im guessing that the error was that it could not create real logic from the code. The error is not the line your pointed to.

Basically the code you have written is testbench code - not synthesis code.

I suggest you try reading the altera or xilinx HDL coding guidlines:

Altera : https://www.altera.com/literature/hb/qts/qts_qii51007.pdf
Xilinx : https://www.xilinx.com/support/documentation/white_papers/wp231.pdf
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top