the delay of a synchronizer

why the delay of a level synchronizer(2 cascaded flip-flop) maybe one period

Hi ,
In the following synchronizer scheme, the synchronized signal is valid in the new clock domain after two clock edges. BUT why the signal delay is between one and two clock periods in the new clock domain, depending on when the input arrives at the synchronizer?

I know that the output of the first flip-flop in the new clock domain may be unstable. And this is why the the second flip-flop in the new clock domain is indispensable. But it is clear that there are TWO flip-flop, which means that the input of the synchronizer should be delayed 2 periods, so I CANNOT understand why the signal delay may be ONE clock periods in the new clock domain.

If it true that the delay is variable, how does this impact timing design?


The attachment talks about crossing the abyss asynchronous sigals in synchronous world, what mostly confuse me in it is the above.

Rogeret

I suggest to draw a timing diagram instead of discussing about words.

If the input signal changes just before the active clock edge, the delay in the first register will be close to zero. The delay in the second register is always one clock cycle.