Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Zubair Alam

  1. Z

    Help with HSPICE and spice

    any idea about how to simulate spice/hspice in cadence?
  2. Z

    Help with HSPICE and spice

    Hi everyone, can anyone state me the difference between hspice and spice syntax? will a hspice netlist be simulated in the spice and vice versa. how to simulate hspice in cadence with spectre. Thanks and regards, Md. Zubair Alam
  3. Z

    Problem calculating delay

    Dear all, I am using a 32nm FET. I have simulated the waves and calculated the delays. But the problem is when i calculated delay(hand calculation) using elmore delay(1st order) model, it doesnt match with the simulation delay. Rather its off by an order of 5(~1e5). :thinker: Is the elmore delay...
  4. Z

    problem with SOI mosfet structure

    You are right. I am not getting where to look and where to start from. Can you point out from where should i begin?or suggest some articles maybe. Thanks @dick_freebird.
  5. Z

    problem with SOI mosfet structure

    Dear all, Can anyone explain in details about soi structure.why it is good/bad.what are the issues with structure.the i-v model for this type of structure. Thanks.
  6. Z

    problem with 32nm feature size of cnfet

    Hi there all, I am having hard time understanding the parameters for a 32nm technology. Can anyone explain please how,why and what should be the device geometry(gate width,gate length,pitch,height etc) I am using stanford CNFET model and i want to simulate in 32 nm feature size. I can varry...
  7. Z

    Problem simulating Veriloga in spectre in cadence

    sorry for the late reply. i guess you are using cadence. 1.go to virtuoso. 2.create a new cell view 3.select cell view type :veriloga 4.then copy the top level module(ncnfet_L3.va) contents/codes in the editor window,parallely go to the veriloga folder and create/copy the files...
  8. Z

    Problem simulating Veriloga in spectre in cadence

    Thanks freebird. I solved the problem. But a new problem has arised:1. with ncnfet,pcnfet i designed some logic gates. but now when i am giving same voltage at vdd(5 V) and gate(5v=logic 1(giving pulses 0 to 5v)) the dc analysis of spectre is not showing logical result.it is showing a ramp.but...
  9. Z

    Problem simulating Veriloga in spectre in cadence

    I have already changed my switch view list and inserted 'veriloga'. In that list there is no 'symbol' or 'CdsSpice'. But when I added veriloga and symbol in that list the simulator ignores the instance and gives the simulation showing only the input.no result for the ncnfet.
  10. Z

    Problem simulating Veriloga in spectre in cadence

    I0 is a ncnfet. But i already created the veriloga view where veriloga.va,NCNFET_L2.va and NCNFET_L1.va files are there. Then I created the symbol and no errors were found. But now when i am trying to use that symbol in circuit the simulation is giving error. What could be the problem??
  11. Z

    Problem simulating Veriloga in spectre in cadence

    Dear all, I have implemented stanford CNFET model in veriloga(no errors found) then made a symbol(no errors found). Then i wanted to use it in circuit(dc sweeping/transient analysis) to see whether the veriloga does what it is supposed to do. When i try to simulate it.it gives me the following...
See more

Part and Inventory Search

Back
Top