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Hi all,
I'm trying to simulate the basic RC circuit with Spetre. Here is my circuit.
I built it with Cadence Virtuoso. But when I try to simulate it in Spectre, it gives me square output just as input, no charging period.
I do select trans, 20ms.
How can I get the right result?
Thanks in...
Hi all,
I'm trying to simulate a current-controlled current source written in veriloga. Here is the code:
// current-controlled current source
// current-controlled current source
module cccs(p,n,pc,nc);
inout p,n;
input pc,nc;
electrical p,n,pc,nc;
parameter real gain=0;
analog...
Hi all,
I just start to learn verilog and try to simulate AND gate on eda playground.
The module is:
module andgate (a, b, y);
input a, b;
output y;
assign y = a & b;
endmodule
And testbench is:
module andgate_tb;
wire t_y;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b)...
Thank you erikl, but it gives me the same errors.
Someone said he solved the same problem by putting the .va file under the original installation directory like \Hspice\Demo\hspice\veriloga\. But I'm using my university's PC and only have read permission for that. Plus, I didn't find we have a...
Hi erikl,
Thank you for your reply. I tried to add "/" at the front but still have the same error. Actually, I tried to delete the ".hdl" line in the netlist file and add a command line " -hdl veriloga.va " in the command. It shows me the same error.
This means it can find my .va file...
Hi all,
I'm trying to simulate a veriloga vccs in hspice.
Here is my veriloga code for vccs:
And here is the netlist
But when I tried to simulate it, it shows me the error :
I googled the error "call to epvaHDLcgen failed.", people said it occurs because of the directory. But my...
UPDATE:
Problem solved. Just use <editor = "gedit"> in CIW without brackets, and reopen the veriloga cellview again... "gedit" can be any editor you like...
Hi all,
I just start to learn verilog-a and want to create a voltage-controlled current source(vccs) in cadence virtuoso. I learned that cadence would check my syntax automatically and create the symbol if the code is OK. However, when I open a new cellview in verilog-a, I can't save the...
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