[SOLVED] Can't create smybol with verilog-a code in cadence

[zongya]

Hi all,

I just start to learn verilog-a and want to create a voltage-controlled current source(vccs) in cadence virtuoso. I learned that cadence would check my syntax automatically and create the symbol if the code is OK. However, when I open a new cellview in verilog-a, I can't save the code, so I can't convert the code to symbol...

When I open the veriloga file it is like this -



Is it because I can open it with only "Read Veriloga"? When I create a new veriloga cellview, the only option is "Read verilog-a".



How can I edit and save the file? help...And thanks in advance!

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UPDATE:
I found when I tried to open verilog-a, it showed me "*WARNING* (icLic-3) Could not get license Virtuoso_Schematic_Editor_L". But when I open a schematic cellview, it showed me the same warning and then "*INFO* (icLic-25) License Virtuoso_Schematic_Editor_XL ("95115") was used to run Schematics L."

That means I have license for Editor_XL. How can I tell cadence to open verilog-a with Editor_XL, not Editor_L?

I google it and found a post said

put it like this into your .cdsinit :

envSetVal("license" "VSELicenseCheckoutOrder" 'string "XL,L")

I opened .cdsinit file and it has many lines...where should i put this additional line??

 

[zongya]

UPDATE:

Problem solved. Just use <editor = "gedit"> in CIW without brackets, and reopen the veriloga cellview again... "gedit" can be any editor you like...