failed to simulate veriloga in hspice

[zongya]

Hi all,

I'm trying to simulate a veriloga vccs in hspice.

Here is my veriloga code for vccs:

// VerilogA for fishy1, asl6, veriloga

`include "constants.vams"
`include "disciplines.vams"

module asl6 (p, n, ps, ns);

inout p, n, ps, ns;
electrical p, n, ps, ns;
parameter g = 1.0;

analog begin

I(p, n) <+ g * V(ps, ns);

end

endmodule

And here is the netlist

** Generated for: hspiceD
** Generated on: Mar 6 13:16:33 2015
** Design library name: fishy1
** Design cell name: asl8
** Design view name: schematic

.vec 'vector.vec'
.include "/opt/cadence/FreePDK45/FreePDK45/ncsu_basekit/models/hspice/hspice_nom.include"
.hdl "home/somnathchakr/vlsix/veriloga.va"

.TEMP 25.0
.OPTION
+ ARTIST=2
+ INGOLD=2
+ PARHIER=LOCAL
+ PSF=2
+ POST=1

** Library name: fishy1
** Cell name: asl8
** View name: schematic



xi2 net5 b a 0 asl6 g=1
r0 net5 b 1

.tran 1p 10n

.END

But when I tried to simulate it, it shows me the error :

*pvaI* system & gcc return code is 512
**error** call to epvaHDLcgen failed.
**error** (Ictest6.sp:25) Definition of model/subckt "veriloga" is not found for the element "xi2". Please specify a defined model/subckt name.

**warning** multiple output options specified, using post

I googled the error "call to epvaHDLcgen failed.", people said it occurs because of the directory. But my directory is correct...I mean "home/somnathchakr/vlsix/veriloga.va" is correct.

Can anyone help me with it? Thanks in advance!

 

[erikl]

"home/somnathchakr/vlsix/veriloga.va" is a relative pathname.
You probably should use an absolute one:
"/home/somnathchakr/vlsix/veriloga.va"

Just a guess!

 

[zongya]

"home/somnathchakr/vlsix/veriloga.va" is a relative pathname.
You probably should use an absolute one:
"/home/somnathchakr/vlsix/veriloga.va"

Just a guess!

Hi erikl,

Thank you for your reply. I tried to add "/" at the front but still have the same error. Actually, I tried to delete the ".hdl" line in the netlist file and add a command line " -hdl veriloga.va " in the command. It shows me the same error.

--------------------------------------------------------
| |
| Synopsys Unified Verilog-A (pVA v2.0) |
| |
| Machine Name: vlsicad2.ecs.umass.edu |
| Copyright (c) 2011 Synopsys Inc., All Rights Reserved. |
| |
--------------------------------------------------------

libepva built by pvamgr synmake_pva_build on Sun May 22 07:53:10 PDT 2011
HSP_HOME: /usr/synopsys/hspice/hspice
HSP_ARCH: linux
HSP_GCC : /usr/synopsys/hspice/hspice/GNU/amd64/gcc-4.2.2-static/bin/gcc
HSP_GCC_VER:
Working-Dir: /home/somnathchakr/vlsix
Args: -p hsp -t spi -f Ictest5.pvadir/pvaHDL.lis -o Ictest5.pvadir


Begin of pVA compiling on Thu Mar 12 10:20:13 2015

Parsing './veriloga.va'
Parsing include file '/usr/synopsys/hspice/hspice/include/constants.vams'
Parsing include file '/usr/synopsys/hspice/hspice/include/disciplines.vams'
Parsing 'veriloga.va'
Parsing include file '/usr/synopsys/hspice/hspice/include/constants.vams'
Parsing include file '/usr/synopsys/hspice/hspice/include/disciplines.vams'
*pvaW* Ignored the duplicated module 'asl6' (veriloga.va:6)

End of pVA compiling on Thu Mar 12 10:20:13 2015


End of build pVA DB on Thu Mar 12 10:20:13 2015

*pvaI* Module (asl6): 4 unexpanded port, 0 init, 1 behav, 1 contrib, 12/0 expr(s)
*pvaI* 0 afCount, 0 fixDIS
*pvaI* Module (asl6): generated 0 flow node(s) during compilation.

End of pVA genC on Thu Mar 12 10:20:13 2015

*pvaI* #### Total 119 line-size(s), 12 expr(s), 1 contr(s), 0 init(s), 1 behav(s), 4 port(s)

Generating Ictest5.pvadir/pvaRTL_linux.so


End of submitting pVA Ictest5.pvadir/pvaRTL.mak on Thu Mar 12 10:20:13 2015

*pvaI* system & gcc return code is 512
**error** call to epvaHDLcgen failed.
**error** (Ictest5.sp:23) Definition of model/subckt "asl6" is not found for the element "xi0". Please specify a defined model/subckt name.

**warning** multiple output options specified, using post


***** job aborted

This means it can find my .va file, and read 'constants.vams' and 'disciplines.vams' in, but cannot find my defined circuit?

 

[erikl]

Instead of

---

Code PHP - [expand]
1
.hdl "/home/somnathchakr/vlsix/veriloga.va"

---

try

---

Code PHP - [expand]
1
.include "/home/somnathchakr/vlsix/veriloga.va"

---

 

[zongya]

Instead of

---

Code PHP - [expand]
1
.hdl "/home/somnathchakr/vlsix/veriloga.va"

---

try

---

Code PHP - [expand]
1
.include "/home/somnathchakr/vlsix/veriloga.va"

---

Thank you erikl, but it gives me the same errors.

Someone said he solved the same problem by putting the .va file under the original installation directory like \Hspice\Demo\hspice\veriloga\. But I'm using my university's PC and only have read permission for that. Plus, I didn't find we have a veriloga folder in the installation directory...