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My question is more basic. How many bits are written to one row in the DDR3?
So, if I'm writing 32 bits at one time, how many writes can I perform till the memory is full?
And if I were written only 16 bits and the bits available in one row is larger, what happens to the last LSBits in the row...
Hi,
my question is as follows, I have a ddr3, 4GB (can be also 8GB, doesn't matter), and I'm saving a 32bit data wide inside.
I want to know if my DDR3 is capable of saving enough number of these 32bit words.
How many of these words can be saved inside?
What is the correct calculation?
Thx!
It will take me forever to explain.
It really doesn't matter, so forgive me.... For my system it does has a meaning.
These are 2 approaches to the problem and I'm wondering if the result will be the same.
One is vector of the differences between the pulses - FFT over it.
The other - FFT over the...
I have a series of pulses (pulse train). I measure the time units between these pulses and log it.
Now I'm doing FFT over these time units (series of numbers: 3000,3050,3020...)
Is there a difference between the fft over these series of numbers and fft over the pulse train? (like in all...
Is there any way to know the VCOM has ended? (by tcl)
Maybe woth IF command, is there a flag VCOM returns after it completed?
My problem is it get stuck in the process even though it ended.
Hi,
I'm running VSIM.exe in a tcl from a software, and output the result to a log file. All works well, except in case there's a compilation error (even simple syntax error in the vhd file), I get this message in the log file:
# Error in macro c:\My_Designs\msim.tcl line 7
#...
Suppose I want to sample low clock freq. (100MHz) signal with a high clock freq. (150MHz). Both siganl are produced at very close freq., only 50MHz difference.
Is the nyquist sampling rate valid here?
I mean, nyquist speaks about sampling an analog signal to a digital one, so when vice versa...
Hi,
I tried to search the forum, but didn't get an answer.
I have a process of 250MHz, of which 62.5MHz is created. I want to cancel it and use a PLL.
Since this is a working design, I need to 'blend in' without making a mess...
My problem is that in the current process of the making of the...
Of course...
What I don't understand is where does it get its filename "tb.sdramddr3_0.open_bank_file.0" from.
It put brackets on it as if it was a filename.
The sdramddr3_0 is the intantiation module name. It is not a filename. The open_bank_file is a function. It is not a filename.
Ok, did it...
now Modelsim shows this:
** Warning: (vsim-3533) [FOFIW] - Failed to open file "e:/user/abc/ddr_sim//tb.sdramddr3_0.open_bank_file.0" for writing.
# No such file or directory
where is it getting its filename from???
Thanks
Thanks for your reply.
First, this directory does not exist, so I created it (didn't help, though), but still - tb.sdramddr3_0.open_bank_file.0, there's no such file. The open_bank_file is a function generated inside ddr3.v file, and it is surely not a filename, so I don't understand how it...
Hi,
I'm trying to simulate the DDR3 along with Micron model in Modelsim but no luck.
I keep getting this error:
# tb.sdramddr3_0.file_io_open: at time 0.0 ns WARNING: no +model_data option specified, using /tmp.
# ** Warning: (vsim-3533) [FOFIW] - Failed to open file...
Hi all,
I'm trying to figure out the relation between Thold and Tcd (hold time & contamination delay) and I'm really confused here.
For example, I read in alot of books that Thold(FF2) <= Tcd(FF1) + Tcd(logic) (the regular example usually shown).
What I don't understand is this: Let's say Thold...
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