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DRC - Design Rule Check
This is specified by the technology and foundrys all over the world give out these
rules for a particular technology. These rules have to be satisfied in any design (physically)
DFM - Design For Manufacturing
Its a pretty much new thing which has been there since the 90nm...
if u want a balanced inverter with a normal skew 2/1 shud be good..as mobility ratios are between 2-3 ...u can use PN ratios for average delay as arnd 1.5....u can hold this ratio and decide the width of ur pmos and nmos based on output fanout/load...
Added after 30 seconds:
And...u can pick...
Re: Extraction of layout
U can use STAR RC as parasitic extractor...get the GDS of the cell that u want to extract and give the GDS as input to STAR RC..it will generate the gds netlist and then run parasitic extractiion...u can also give circuit netlist to get accurate results..extractor will...
May be borderless means with power mesh structure ( VDD,VSS mesh over the SRAM) and with border means with power ring structure (VDD,VSS ring around the SRAM)
I guess so..
Can anyone please tell me how to extract bent poly resistance..?
I have been trying to extract it through STAR RC but with no success..
Please help....Thanks ...
Re: skill language
SKILL is a scripting language developed by CADENCE and forms almost the base for all their software tools. The ICFB /Virtuoso tool is written fully in SKILL. All the GUI that is shown in Virtuoso are nothing but SKILL functions running in the background.
It is similar to any...
STAR RC will extract the cap of all the nets in your design. It needs GDS and circuit file for extracting , actually speaking circuit file is not neccessary but people suggest to make it LVS clean and then extract. But if you are extracting some matching or analog devices, i would suggest you to...
Re: EM
EM is Electromigration. which determines the maximum current that can carried by a metal line for a period of time. Usually there are three important currents that we calculate for EM, peak current, RMS current and the DC current. Almost all the relations between current and metal width...
1mA=1um rule doesn't hold these days...you need to calculate the currents and use your foundry equations to find out the width you need ...
If u cannot access foundry documents, better search for good tools which can point out EM violations...( they too need some tech files :))
sram critical path
Rabey/Kang discusses about the memory blocks in detail and gives a good idea...but i think once you start doing a critical path, you will learn more with experience.
Just check the attachment - gives u some insight into RAM architectures and blocks
stream in multiple gds files into cadence at once
You can write a SKILL(language in Cadence OPUS) program to stream in all your GDS files into one library. ex: absImportGDS , use your GDS list along with this function to import all the GDS files. For more information Check TOOLS>SKILL...
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