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Current & Metal size

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ryusgnal

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Is it true that the larger current flow in the circuit, the larger width of metal we need to used? if i'm using 0.18um technology, what is the suitable width of metal i have to use for 2.6mA current? My circuit will function in 477MHz frequency.
 

You need to do Electromigration analysis on your design. You will need to calculate the
RMS current of the signal if the signal is a switching signal and DC current if it is a stable current. Calculate the currents and check your Design Rule Manual guide for the Electromigration equations ( current & width dependents) . Substitute the currents in the equation and calculate the width required for your metal and number of VIAS needed for connection. An approximate method to calculate the width required is to calculate the average current by the formula CVF ( capacitance*voltage*frequency)
.With the help of average current and current required for metal width minimum and metal width 1um, you can find the approximate metal width required for your signal.
 

I agreed 1ma=1ua width of metal, but top metal current density is bigger than that.
You need to refer design rule of what you targeted process, such as TSMC.
 

why don't find these parameters in your foundry's file.
 

Am i need to build larger source and drain area for larger current flow in the transistor?
 

Hi,
We look through our process manual to find the current density capability for this wire. We see that the metal we want to use can handle 0.5 milliamps per micron. That number tells us that we need to make that wire a minimum of 2 microns wide if we expect it to handle 1 milliamp.
Thanks!
 

1mA=1um no longer exists down from 0.35um process. Always check from foundry's document for this rule.
 

hung_wai_ming(at)hotmail.com said:
1mA=1um no longer exists down from 0.35um process. Always check from foundry's document for this rule.

I agree with you because i think 1mA=1um is too big for 0.18um. do you have any idea or suggestion besides checking from foundry's document? because i don't have the document. thank you.
 

Which process you are using?
Top metal TS*C 0.25um logic process is 1.6mA/1um (110C)
Top metal C*M 0.18um mixed process 1.0mA/1um

Anyway, it varies and it depends on your metal layer and metal thickness, there are lots of metal thickness for process down to 0.18um
 

1mA=1um rule doesn't hold these days...you need to calculate the currents and use your foundry equations to find out the width you need ...
If u cannot access foundry documents, better search for good tools which can point out EM violations...( they too need some tech files :))
 

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