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Hi all,
My design includes some RAMs, for Place&Route stage, I need the physical libs of RAMs to be the Reference Libs.
As far as I know, if I have LEF file and GDSII file of a RAM, I can use these files to build a milkway, then it's all done.
But now, my free-version memory compiler cannot...
Hi all,
I'm using Artisan Memory Compiler to generate files, but all formats are ok except GDSII/LVS Netlist.
Do these two formats require special Licenses? Or they need some special setup?
Thanks in advance.
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