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Fir filter tap
Hello everyone:
I need some help about my problem :
Now I use a FIR filter IP core of xilinx. This filter is used for a 12 bit DAC.
The filter is low pass filter .It's taps is 39 and input data width is 12. I want to put a 12 bit dac directly connected to the output...
My data converter is AD9863. My ADC sample clock is souced from FPGA.
The sample clock from FPGA isn't clean. The ADC sample clock frequecy is 15Mhz.I find that noises are introduced into my system. I have some problems about Clock. The sample clock can be sourced from FPGA?If not,how can I...
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